What is the best and worst case latency for interrupts on the LS1043A? Latency between the occurrence of the interrupt and the start of the ISR.
There is some description about the timings of interrupt signaling in the GIC-400 with physical interrupts, in GIC-400 RM.
This is an example, take SPIs and two level-sensitive N and M interrupts, the former with higher priority as example:
In Figure B-1, the latency at the physical interface is tph = 15 clock cycles.
The Distributor takes several cycles to calculate the highest priority pending interrupt. If an interrupt becomes pending while the calculation is in progress, it only affects the results of the next calculation. This means that the interrupt latency might vary. Therefore, while tph is typically 12 cycles, it might often be between 10 and 20 cycles.
The timings in Figure B-1 are for illustration only. They are typical values that are not guaranteed and must not be relied upon.
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