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MK10 MCG Clock Configuration

Question asked by Brian Cook on Jun 21, 2016

I am migrating from an MK40 to an MK10 part and am having issues configuring the PLL correctly (I do know about the 2x frequency going into the FLL. My board has an 8MHz osc (OSC0) and I want to program a 96MHz MCGOutClk.  To generate this, I have used the following settings:

C1: FRDIV=3, CLKS=2

C2: ANGE0=1, HGO0=1 EREFS0=1

C5: PRDIV0=0

C6: VDIV0=8, PLLS=1

When I set these parameters, using VDIV=8, the code generates a hardware fault.  If I set VDIV=7, the code runs, but I end with McgOutClk=92MHz, which isn't what I want.  My code is including MK10F12.h from KDS SDK 1.3.0.  I've hardcoded the values to make the code easier to read.  The part that is on the board is a MK10FN1M0VMD12.

 

 



Original Attachment has been moved to: bsp_interface.cpp.zip

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