T4240:serdes PCS:How to configure it?

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T4240:serdes PCS:How to configure it?

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carlpeng
Contributor II

Hello,

I have some confusion on PCS configuration of T4240.

My questions is as below:

1. How to configure PCS of each serdes lane?

    Does configure it through corresponding MAC's MDIO register?

2. lane1 PCS can only be configured by MAC1 according to the below MDIO port mapping?

3. Using MAC9 to configure lane6 of serdes, not using MAC7?

    That is to say, if I choose sg2.3 option, and choose serdes lane 6, I need to use MAC9 to

    configure PCS of serdes lane6, use MAC3 can not configure it?

4. EMI can only access external phy connected with serdes, not used to access PCS of

   serdes?

5. SGMIIACR1[MDEV_PORT] need to configured, can it be all set as 0?

    From the context, when use MAC MDIO to access corresponding PCS, hardware will

   compare the phy addr in the COMMAND with the corresponding MDEV_PORT, then

   decide whether access the PCS, so does this field must be assigned?

Thank you!

As the T4240RM.pdf said as follow.

pastedImage_0.png

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carlpeng
Contributor II

Hello Ufedor,

Does the SGMIIn correspond with MAC?

That is to say, if I choose a MAC, then means that I have choose the corresponding SGMIIn,

no related with lane?

Thank you!

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carlpeng
Contributor II

Hello Ufedor,

Thanks a lot !

But I really do not understand the MDIO port mapping table.

What does the  "n" of SGMIIn means? Does it correspond with physical pins?

if it does not correspond with physical pins, The a, b, c, d, e, f, g, h mean what?

pastedImage_0.png

Thank you!

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ufedor
NXP Employee
NXP Employee

> if it does not correspond with physical pins, The a, b, c, d, e, f, g, h mean what?

It does not correspond with physical pins.

It is a  one letter index of the SGMII PCS.

> Does the SGMIIn correspond with MAC?

> That is to say, if I choose a MAC, then means that I have choose the corresponding SGMIIn

Yes.

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carlpeng
Contributor II

Thanks Ufedor!

But I still have a question, could you please help to give some comments?

What is the relationship between SGMIIn and Lanex?

For example,

Does SGMIIa means that it uses laneA? if does not, then SGMIIa means what?

Thank you!

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ufedor
NXP Employee
NXP Employee

> Does SGMIIa means that it uses laneA?

No.

> if does not, then SGMIIa means what?

SGMII PCS "a" - refer to the T4240 RM, 18.1.1.6 MDIO port mapping.

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ufedor
NXP Employee
NXP Employee

1) Yes, Each PCS MDIO is driven by the corresponding MAC's MDIO.

Please consider the following interconnect diagram:

SerDes lane <-> PCS <-> MAC

where PCS could be SGMII, QSGMII and XFI according to the selected protocol.

2) Lane1 of which SerDes?

Example:

For the SerDes1 LaneA SGMIIe PCS is controlled by FM1 MAC5 MDIO.

3) The sg2.3 means that FM2 MAC3 is controlling the SGMIIc PCS.

4) Yes.

5) Yes.

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