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P2020 WE* and CS* during a HRESET* condition being asserted?

Question asked by Nen Wen Soh on Jun 19, 2016
Latest reply on Jun 21, 2016 by Bulat Karymov

Can I know what are the states of WE* and CS* during a P2020 HRESET* condition?

From the datasheet, it is stated that most signals are tri-stated. Upon probing the signals using an oscilloscope, I have noted that WE* and CS* are asserted low even though I have pull up resistors while they are in hardware reset. Why is this so?