I am using the FRDM-K64F evaluation board since a while, and have achieved already a lot with it, using the SD card, two UARTS in parallel, USB, numerous GPIOs etc. It is a remarkable piece of hardware, especially considering the low price which is important for me in a university environment which will not buy 100000 pieces, and therefore I am quite grateful for it and the software that comes with it. The new SDK2 is so-so, too formal and too many levels of #defines for my taste, but ok. But now I am really struggling with the Pulse Width Modulation (PWM) on the Timer Module. My job is comparatively simple, I want to use FTM3 channels 0+1 in combined mode to produce an asymmetric PWM, and channels 2+3 for another PWM at the same base frequency but different duty cycle. I would not have thought that this is so difficult.
All examples that I found use interrupts, which I don't want to do, there will be more than enough interrupts in the final application and a PWM should really work without them.
There is no sample program in the SDK (as opposed to most other modules), only the "bubble.c" which apparently also uses interrupts.
The SDK functions do not work.
Trying to set the registers directly brought me a little further, after I found out that I have to enable a certain well-hidden clock first, which I found out only by serious debugging but not after reading several time Chapter 40 ("FlexTimer Module") of the chip manual. The SDK documentation is unreadable for humans in that respect. Most registers seem to be set ok now by directly setting bits with hex numbers, avoiding the SDK. But still I cannot set the most relevant ones, the FTM3_CnV registers that are supposed to hold the thresholds. I have no clue whether this is due to the mysterious WPDIS and WPEN bits which are described as bit 2 of the FTMx_MODE register :
WPDIS Write Protection Disable
When write protection is enabled (WPDIS = 0), write protected bits cannot be written. When write
protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the negation of
the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1
and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
0 Write protection is enabled.
1 Write protection is disabled.
and as bit 6 in the FTMx_FMS register:
WPEN Write Protection Enable
The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared
when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect.
0 Write protection is disabled. Write protected bits can be written.
1 Write protection is enabled. Write protected bits cannot be written.
This is highly confusing. But maybe I am also doing something wrong with the PWM SYNC features which are equally confusing and even less described.
I would be very grateful if you could point me to a working example of "combined mode" PWM operation without interrupts.