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Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

Question asked by a a on Jun 20, 2016
Latest reply on Jun 26, 2016 by Timesys Support

When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting?

And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ?

Is Systick equals to cycle? Because I measured instruction NOP, it takes 6 systicks