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Android lag and LVDS flicker on i.MX6 dual display setup

Question asked by Valts Blukis on Jun 17, 2016
Latest reply on Jun 23, 2016 by Valts Blukis

I am trying to get dual display support working for Android 5.1.1 for a device based on Variscite VAR_SOM_MX6 with i.MX6 Dual.
I have a 1280x800 panel on LVDS0 and an HDMI port that I intend to drive at the same resolution. I have managed to get Android displayed in mirror mode on both displays, but when HDMI is plugged in, Android becomes very sluggish (framerate may be around 5fps) and the LVDS panel starts to flicker as if the clock frequency was wrong.


I also tried this on i.MX6 Quad and I set hdmi_core to ipu_id = <1> to use the other IPU, but the result was the same.

I have spent multiple days experimenting with this but I can't find a configuration that doesn't lag. Either LVDS or HDMI works smoothly with no lag.


Any help would be greatly appreciated! I am getting desperate by now with a tight deadline on this.


I use the following bootargs:

console=ttymxc0,115200 init=/init video=mxcfb0:dev=ldb,bpp=32 video=mxcfb1:dev=hdmi,1280x720M@60,if=RGB24,bpp=32 video=mxcfb2:off video=mxcfb3:off fbmem=24M vmalloc=400M androidboot.console=ttymxc0 consoleblank=0 androidboot.hardware=freescale cma=384M androidboot.selinux=disabled androidboot.dm_verity=disabled


And these are relevant fragments of the board device tree:


&hdmi_core {

  ipu_id = <0>;

  disp_id = <1>;

  status = "okay";



&hdmi_video {

  fsl,phy_reg_vlev = <0x0294>;

  fsl,phy_reg_cksymtx = <0x800d>;

  status = "okay";



&ldb {

  status = "okay";


  lvds-channel@0 {

     fsl,data-mapping = "spwg";

     fsl,data-width = <24>;


     status = "okay";



         native-mode = <&timing0c>;

         timing0c: hsd100pxn1 {

             clock-frequency = <72000000>;

             hactive = <1280>;

             vactive = <800>;

             hback-porch = <39>;

             hfront-porch = <39>;

             vback-porch = <29>;

             vfront-porch = <13>;

             hsync-len = <47>;

             vsync-len = <2>;






&ldb {

  lvds-channel@0 {

    crtc = "ipu1-di0";




&mxcfb1 {

  status = "okay";



&mxcfb2 {

  status = "okay";



Some relevant lines from the boot log:


ccm: ldb_di_sel already changed from reset value

failed to set parent of clk ldb_di0_sel to pll5_video_div: -38

failed to set parent of clk ldb_di1_sel to pll5_video_div: -38

failed to set parent of clk gpu2d_core_sel to pll2_pfd1_594m: -22

Switching to timer-based delay loop

sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655765682ns

Console: colour dummy device 80x30

Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)

pid_max: default: 32768 minimum: 301


mxc_sdc_fb fb.25: registered mxc display driver ldb

imx-ipuv3 2400000.ipu: IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)

Console: switching to colour frame buffer device 160x50

mxc_hdmi 20e0000.hdmi_video: Detected HDMI controller 0x13:0x1a:0xa0:0xc1

fbcvt: 1280x720@60: CVT Name - .921M9

mxc_sdc_fb fb.26: registered mxc display driver hdmi

imx_epdc_fb 20f4000.epdc: can't get/select pinctrl