I would like to ask about the timing of WEIM of i.MX25.
My customer is using i.MX257 WEIM interface to connect external SRAM with asynchronous mode. And they have following questions on its timing control.
Could you give answers to the following questions?
Inside the CPU, when is the input data captured?
According to datasheet, the following description is seen.
“Input data, ECB and DTACK are all captured relative to BCLK rising edge.”
As a specification of i.MX25, the capturing is done relative to BCLK rising edge.
And inside of i.MX25, the data capturing occurs relative to HCLK.
Am I correct?
The customer wants to know the exact number of data hold-time and setup-time for reading from the external SRAM.
In datasheet(IMX25CEC, Rev.10), Figure-45, it seems to be corresponding to WE43 and WE44. As for WE43, it is mentioned as ‘MAXCO – MAXCSO + MAXDI’ in datasheet.
Could you show me how one can calculate the number of WE43?
The customer wants to know where they can get the number for MAXCO, MAXCSO and MAXDI.
The customer believes that they should tune up WSC setting depending on SRAM access timing. Could you show me which timings are affected by the number of WSC?
They think that the release timing of CS and OE is affected by WSC setting.
Is ti true?