Question, i.MX25 WEIM access timing

[Aemj]

Dear team,

I would like to ask about the timing of WEIM of i.MX25.

My customer is using i.MX257 WEIM interface to connect external SRAM with asynchronous mode. And they have following questions on its timing control.

Could you give answers to the following questions?

(1)

Inside the CPU, when is the input data captured?

According to datasheet, the following description is seen.

“Input data, ECB and DTACK are all captured relative to BCLK rising edge.”

I think;

As a specification of i.MX25, the capturing is done relative to BCLK rising edge.

And inside of i.MX25, the data capturing occurs relative to HCLK.

Am I correct?

(2)

The customer wants to know the exact number of data hold-time and setup-time for reading from the external SRAM.

In datasheet(IMX25CEC, Rev.10), Figure-45, it seems to be corresponding to WE43 and WE44. As for WE43, it is mentioned as ‘MAXCO – MAXCSO + MAXDI’ in datasheet.

Could you show me how one can calculate the number of WE43?

The customer wants to know where they can get the number for MAXCO, MAXCSO and MAXDI.

(3)

The customer believes that they should tune up WSC setting depending on SRAM access timing. Could you show me which timings are affected by the number of WSC?

They think that the release timing of CS and OE is affected by WSC setting.

Is ti true?

Thanks,

Miyamoto

[Yuri · Accepted solution]

Hello,

Please look at my comments below.

1.
  Yes, BCLK is derivative of (internal) HCLK and internal clock

is used to sample data by i.MX25 internal master. “In the typical
case the input data is not sampled by the WEIM, but it is sampled
by the AHB master on the rising edge of HCLK when HREADY is high.”

2.

  Note, some WEIM timings are software configurable.
The Datasheet provides mainly hardware (min / max) values.

  For i.MX25

MAXCO: 5.5ns

MAXCSO: 5.6ns

MAXDI: 2.8ns

  Also, setup and hold parameters relate to sync accesses, assuming timings

relatively clock edge(s). 

3.
  WEIM access time is defined by the WSC parameter. Really it defines sample point

in read operation. This parameter should be set to a value enough for SRAM access,

using SRAM hardware specs.

Have a great day,
Yuri

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[Aemj]

Hi Yuri,

Sorry for my late response, but the customer wants to clarify about the WEIM timing based on Figure 49-7 written in i.MX25 reference manual.

Please find the attached file.

In the file, the confirmation is written on the Figure 49-7.

Could you please give your comments to the clarification?

(1)

Can I understand that 1 HCLK cycle is inserted when WSC=1?

(2)

Is there any specification about the time from the start of HCLK to the CS valid?

According to this chart, can I understand it is half of HCLK cycle?

(3)

Please let me clarify about the sampling timing. Is the data sampling timing at here?

Can I understand that WSC setting can adjust the timing of the sampling which is done at the rising edge of HCLK?

Best Regards,

Miyamoto

[Yuri]

Hello,

  Please look at my comments below.

1.

> Can I understand that 1 HCLK cycle is inserted when WSC=1?

  When WSC=1, 1 HCLK cycle is access time.

WSC sets the total cycle length (number of HCLK cycles to do access).

2.
> Is there any specification about the time from the start of HCLK
> to the CS valid?

> According to this chart, can I understand it is half of HCLK cycle?

  Please refer to i.MX25 Datasheet, WEIM Bus Timing Parameters table,

WE6 - Clock rise/fall to CS[x] valid. Also (programmable) CSA parameter

should be taken into account. Its granularity is half of HCLK.

3.

> Please let me clarify about the sampling timing. Is the data sampling
> timing at here?

> Can I understand that WSC setting can adjust the timing of the sampling

> which is done at the rising edge of HCLK?

  Correct.

Regards,

Yuri.