lpc1343 Random Questions

lpcware · ‎06-15-2016

Content originally posted in LPCWare by ub3r on Wed Jan 25 10:31:55 MST 2012
High guys,

I couldnt find any info on the 1343 ADC KSPS in the datasheet. What is the maximum KSPS at 10bit and 8bit?

Also, can we generate an interrupt at the end of each duty cycle on timer16_0 ? If so.. How??

cheers
Tony

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Ex-Zero on Thu Jan 26 04:06:00 MST 2012

Quote: ub3r
Therefore, if i want a falling edge interrupt, shouldn't i interrupt when TC = MR0??
The settings you gave me are for MR3, hence end of period, not falling edge.

No, reset (MR3) = low, MRx = high :) MR0 is your low time :rolleyes:

With MR3 = 100 and MR0 = [COLOR=Red]75[/COLOR] you're generating a [COLOR=Red]25[/COLOR]% high signal :eek:

User manual:

Quote:

15.8.13 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go [COLOR=Red]LOW at the beginning of each PWM [/COLOR]cycle (timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go [COLOR=Red]HIGH when its match value is reached[/COLOR]. If no match occurs (i.e. the match value is greater than the PWM cycle length), the PWM output remains continuously LOW.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by ub3r on Thu Jan 26 00:45:33 MST 2012
Hi Zero, Your the man. :D

But just a question.
I set my PWM duty cycle by loading a value in MR0, and the period is set by MR3.

Therefore, if i want a falling edge interrupt, shouldn't i interrupt when TC = MR0??

The settings you gave me are for MR3, hence end of period, not falling edge.

regards
Tony

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Ex-Zero on Wed Jan 25 22:33:21 MST 2012
That's easy

Enable MRx interrupt, here MR3 interrupt in MCR:

LPC_TMR16B1->MCR   = (1<<10)|(1<<9);          //MR3 reset, MR3 interrupt
...
NVIC_EnableIRQ(TIMER_16_1_IRQn);            //enable interrupt

and add interrupt handler:

void TIMER16_1_IRQHandler(void)
{
 if (LPC_TMR16B1->IR &(1<<3))      //detect interrupt MR3
 {
  LPC_TMR16B1->IR = (1<<3);        //clear interrupt
  LED_TOG;                         //toggle output to see something working...
 }
}

Note: PIO1_9 Match bit is 0, so it should be: LPC_IOCON->PIO1_9 |= (1<<0); //PIO1_9 MATCH output :rolleyes:

lpcware · ‎06-15-2016

Content originally posted in LPCWare by ub3r on Wed Jan 25 19:52:40 MST 2012
Woah!! Cant believe i didnt see that 400Ksps.

Anyways, my current Pwm Config looks like this:

void setPWM(void)
{
// We cant use MR2 for PWM because the pin is used for JTAG

LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);  // Enable clock to timer 1 CT16b1
LPC_IOCON->PIO1_9         |= (1<<1);// Enable Match Mode for PWM

LPC_TMR16B1->MCR |= (1<<10);       // Reset at MR3
LPC_TMR16B1->MR0 = 0;        // Match register 0

LPC_TMR16B1->MR3 = 10000;        // Match register 2 - cycle length
LPC_TMR16B1->PWMC |= (1<<1);   // PWMC register -MAT0 is PWM.

LPC_TMR16B1->TCR = 1;   // Enable timer 16-1
}

Basically i want to add an interrupt to trigger when at the falling edge of the duty cycle. Dont know how though.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Ex-Zero on Wed Jan 25 10:53:39 MST 2012

Quote:

I couldnt find any info on the 1343 ADC KSPS in the datasheet.

:confused:

Quote:

7.13.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD.
• 10-bit conversion time >= 2.44 µs (up to 400 kSamples/s).

Quote:

Also, can we generate an interrupt at the end of each duty cycle on timer16_0 ? If so.. How??

Which duty cycle are we talking about? Perhaps Match control register?