Content originally posted in LPCWare by roger.esoft on Sun Feb 05 09:34:26 MST 2012
[FONT=Verdana][SIZE=2]Hi,
[/SIZE][/FONT][FONT=Verdana][SIZE=2]I'm trying to configurate the Canbus bit timing too, and I've the same question. I would like to know if TSEG1 register includes the TPROP_SEG value.
I'm trying to adjust the controller to my system requirements, where length is the most important thing. I'm using this configuration:[/SIZE][/FONT]
[FONT="]System clock f_sys = 48 MHz.
System clock period t_sys = 1/f_sys = 20,833333 ns.[/FONT]
[FONT="]Bit rate prescaler (BRP) =16
CAN time quantum [B]tq = t_sys*16 = 333,3333ns[/B] (at [B]BRP = 16[/B])[/FONT]
[FONT="]El nº de timequanta ha d’estar entre [B]8..25[/B].[/FONT]
[FONT="]
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[FONT="]Desired bit rate is 125 KBit/s, desired bit time is thus 8000 ns.
Actual bit time = [B]24[/B] tq = 7999,992 ns
Actual bit rate is [B]125,125[/B] KBit/s[/FONT]
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[FONT="]CAN bus length = 550 m, with 5 ns/m signal delay time.[/FONT]
[FONT="]My transceiver loop delay = 245ns
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[FONT="] Propagation delay time : 2*transceiver loop delay + bus line delay = 3000 ns
(maximum loop delay between CAN nodes)[/FONT]
[FONT="]
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[FONT="]Each bit transmitted on a CAN network has 4 segments (Sync_Seg, Prop_Seg,Phase_Seg1, and Phase_Seg2). The sum of these segments determines the CAN bit time (1/bit rate).
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[FONT="]
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[FONT="]Prop_Seg = 10 tq = [B]3333,333 ns[/B] ( >= 3250 ns).
Sync_Seg = 1 tq = [B]333,333 ns[/B][/FONT]
[FONT="]Phase_seg1 + Phase_Seg2 = (24-11) tq = 13 tq
Phase_seg1 <= Phase_Seg2, => Phase_seg1 = 9 tq and Phase_Seg2 = 4 tq
SJW = (min(Phase_Seg1, 4) tq = 4 tq[/FONT]
[FONT="]
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[FONT="]TSEG1 = ([B][COLOR=Red]Prop_Seg[/COLOR][/B] + Phase_Seg1 - 1) = [COLOR=Red][B]19[/B][/COLOR]
TSEG2 = (Phase_Seg2 - 1) = 3
SJW_p = (SJW - 1) = 3[/FONT]
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[FONT="]It couldn't be this value, is not allowed. So I only can think this is not TSEG1 not includes Prop_Seg.[/FONT]
[FONT="]So TSEG1 = (Phase_Seg1 - 1) = [COLOR=Black]8[/COLOR][/FONT][FONT="]
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I'll try this and tell if it is
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