lpcware

nvic priorities mapped in core_cm3.h

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by dragilla on Fri Jan 20 01:52:51 MST 2012
Hey, I'm trying to connect the user manual with the code I find in the core_cm3.h. I use the cmsis1.3 example code to initialize the uart0 interrupt. LPC1769.

The code goes like this:

    /* preemption = 1, sub-priority = 1 */
    NVIC_SetPriority(UART0_IRQn, ((0x01<<3)|0x01));

The NVIC_SetPriority sets the value of NVIC->IP[(uint32_t)(IRQn)] (which in this case is 5) to 72 (01001000).

What the hell does that mean? :)
There are 9 priority registers described in the UM. Each has 5 peripherals, each peripheral has a 5 bit priority (0-highest, 31-lowest).
This gives me 9(registers)*5(peripherals)*5(bits) = 255 bits.
But the NVIC->IP is 240 bytes... why?

What does it mean to set NVIC->IP[5] to value 01001000 ? What's the priority here (in the scale described in the UM)?

What's the preemption (mentioned in the comment in the example code)?
In the UM, the preeption is only described in the context of exceptions.

Please help me understand.

regards,

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