nvic priorities mapped in core_cm3.h

[lpcware]

Content originally posted in LPCWare by dragilla on Fri Jan 20 01:52:51 MST 2012
Hey, I'm trying to connect the user manual with the code I find in the core_cm3.h. I use the cmsis1.3 example code to initialize the uart0 interrupt. LPC1769.

The code goes like this:

    /* preemption = 1, sub-priority = 1 */
    NVIC_SetPriority(UART0_IRQn, ((0x01<<3)|0x01));

The NVIC_SetPriority sets the value of NVIC->IP[(uint32_t)(IRQn)] (which in this case is 5) to 72 (01001000).

What the hell does that mean?
There are 9 priority registers described in the UM. Each has 5 peripherals, each peripheral has a 5 bit priority (0-highest, 31-lowest).
This gives me 9(registers)*5(peripherals)*5(bits) = 255 bits.
But the NVIC->IP is 240 bytes... why?

What does it mean to set NVIC->IP[5] to value 01001000 ? What's the priority here (in the scale described in the UM)?

What's the preemption (mentioned in the comment in the example code)?
In the UM, the preeption is only described in the context of exceptions.

Please help me understand.

regards,

[lpcware]

Content originally posted in LPCWare by dragilla on Mon Dec 31 05:04:10 MST 2012
Hello again. After a longer while I'm back at this topic. Still can't figure it out. Maybe this time someone can help me grasp it?
I'm not sure what priorities I give and it is quite important after all :)

edit: ok, there is a mistake in my calculations in first post. There are 4 interrupts in each register. So it's 9*4*5 = 180 bits. Or 32 bits (register size) * 9 registers = 288. It's not 240 no matter how I try to calculate.

However NVIC->IP[5] is what one's suppose to use when setting the priority for UART0 (UART0_IRQn is defined as 5 in LPC17xx.h) and UART0 is fifth (calculating from 0) interrupt in the IPR registers (it is in second position in second register). Another example of matching (kind of) is RIT_IRQn (which I also happen to use) with number 29 (also 29th in registers). There are 35 iterrupts in IPR regs and 35 indexes (0-34) defined in LPC17xx.h.

I still don't understand. Maybe some guide or clue please? How to debug this?

[lpcware]

Content originally posted in LPCWare by dragilla on Fri Jan 20 09:18:09 MST 2012
Maybe I'm not making my self clear enough... I know how (or at least I think I know) to set up a priority for an interrupt. I simply give its name and priority from 1 to "(1 << __NVIC_PRIO_BITS) -1" as parameters to NVIC_SetPriority function.

What I don't know is how the function sets the registers. I wanna know how it works - it doesn't seem to be right just reading the source code and the UM.

Anyone please?