lpcware

LPC1769_100MHz core clock (?)

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by timos2302 on Mon Jun 20 15:07:40 MST 2011
[FONT=Century Gothic]Dear friends
I have read the UM datasheet, the blinky example, the timers example e.t.c , even the xls calculator given by NXP for calculating M, and N portions of the 32bit register configuration for the PLL0.

So i collected 3 questions/notes (sorry if they seem to childish for some of you)

-1- The M and N values that the xls calculator exports are true or the UM is true that says in small letters >>>>  N-1,  M-1   ? ? ?

-2-Suppose i want a 100MHz core clock >> AFTER the prescaller of the main clock, What on earth are your M and N values and prescaller settings with a 12MHz external clock ? I managed core clock (cclk) only up to 33.3MHz (cclk/3 - 100/3 - the /1 and /2 values are forbiden as i read).

-3- Is there a magic tool in excel or VB or something so i can get my hex value of the PLL0CGF register at once , and not breaking my head to combine the M,N portions and some dummy bits of this 32bit register, then converting in binary, then converting it into a hex monsterous byte?

Thanks all for your kind patience
Sincerely,
Timothy

(newbie to ARM's . . .:o comming from the AVR "poor" 8bit world)[/FONT]

Outcomes