Ken Macfarlane

"misaligned long address access"/ cpu int 5, generated by Processor Expert

Discussion created by Ken Macfarlane on Jun 3, 2008
Latest reply on Jul 17, 2008 by Processor Expert
Freescale 56f800 DSP & Codewarrior v8.2
 
I am trying to convert a working single tasking application to sit on top of uCos. An interrupt samples an ADC every time a pulse goes by. The pulse rate is 200kHz, and the single tasking code handled this. Under uCos, it works with 1 Hz pulses, but the main task slows down as the pulse rate goes up. With pulse rates of 100Hz, the application hangs after hitting cpu interrupt 5 in cpu.c (code generated by processor expert), the error message for which is "misaligned long address access". The interrupt disables itself until the ADC has had time to finish conversion i.e. the ADC On completion event re-enables the IRQ, so the interrupt shouldn't fire before the first one finishes. Servicing each pulse takes 0.5 millisecs from a scope & led measurment, but the ISR itself is much shorter - usecs, although I haven't measured it yet.
 
Anybody know anything more about what might cause "cpu interrupt 5"? I can't find any mention of it in the Processor Expert documentation.
 
 

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