Problem with SSP on LPC1769

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by ngoncalves on Mon Mar 05 14:34:56 MST 2012

I am trying to configure and use the SSP1 peripheral of an LPC1769 for an SPI bus, with 8 bits data and 8 ~ 10 MHz bus clock. The processor is the slave of the bus and I want it to partially emulate the behavior of a flash memory.

I know the SPI protocol, but I cannot find the options I need for the SSP1. First, there does not seem to exist an interrupt for when a byte was received. Only for a reception time-out (a byte is available but has not been read after x milliseconds/microseconds) and for the reception FIFO being at least half full.

Second, so far I am only able to read the first byte sent by the master. I tried poolling the Receiver Not Empty bit (RNE), and enabling all interrupt sources. But I cannot get more than one byte. It seems reading the data register does not remove the byte from the reception FIFO.

My processor is running at 100 MHz, and that is the frequency of the SSP1 peripheral clock. I am then pre-scaling by 120 to get a little over 8 MHz. Is this correct ? The datasheet says that the bus clock must be at most 1/12 of the peripheral clock for the SSP1 as slave. Is 8 MHz too high ?

How can I read multiple bytes ? For some reason, pooling the RNE status bit does not work and I can't find an interrupt for receiving a byte.