Problem with SSP on LPC1769

[lpcware]

Content originally posted in LPCWare by ngoncalves on Mon Mar 05 14:34:56 MST 2012
Hello,

I am trying to configure and use the SSP1 peripheral of an LPC1769 for an SPI bus, with 8 bits data and 8 ~ 10 MHz bus clock. The processor is the slave of the bus and I want it to partially emulate the behavior of a flash memory.

I know the SPI protocol, but I cannot find the options I need for the SSP1. First, there does not seem to exist an interrupt for when a byte was received. Only for a reception time-out (a byte is available but has not been read after x milliseconds/microseconds) and for the reception FIFO being at least half full.

Second, so far I am only able to read the first byte sent by the master. I tried poolling the Receiver Not Empty bit (RNE), and enabling all interrupt sources. But I cannot get more than one byte. It seems reading the data register does not remove the byte from the reception FIFO.

My processor is running at 100 MHz, and that is the frequency of the SSP1 peripheral clock. I am then pre-scaling by 120 to get a little over 8 MHz. Is this correct ? The datasheet says that the bus clock must be at most 1/12 of the peripheral clock for the SSP1 as slave. Is 8 MHz too high ?

How can I read multiple bytes ? For some reason, pooling the RNE status bit does not work and I can't find an interrupt for receiving a byte.

Thanks,

   Nelson

[lpcware]

Content originally posted in LPCWare by ngoncalves on Tue Mar 06 09:58:40 MST 2012
I think I found the source of the problem. It seems the SSP, in SPI incarnation, requires the SSEL line to be toggled once per byte.

http://www.lpcware.com/content/forum/ssp-port-problem-spi-mode

Since my bus master mantains the SSEL line low for the entire session, the LPC1769 could not read or write....

I am going to give up and just bit-bang the SPI protocol. I know there is an SPI port available, but it shares pins with the serial port which we are already using and right now a new re-design of the pcb's is just not feasible.

[lpcware]

Content originally posted in LPCWare by ngoncalves on Tue Mar 06 09:43:26 MST 2012
I am looking at the SPI bus with a logic analyzer. The MOSI line shows the bytes being sent by the master. But the MISO line is always low. Which explains the LPC1769 cannot output data.

I know there is the SOD bit in the CR1 register, but I have set it to zero to disable it.

I am running out of ideas. Help please ....

[lpcware]

Content originally posted in LPCWare by ngoncalves on Tue Mar 06 08:58:53 MST 2012
This just keeps getting stranger and stranger.

If I try to read a byte, I only get the first one. I tried changing the peripheral clock, enabling the pull-up on the SSEL line and just about anything else I can think of. But it never works.

If I write a byte, it blocks trying to send the byte. The BUSY bit on the status register never goes to zero.

I checked against the code examples I found in the forum, and I am setting up the SSP peripheral correctly. Or so I believe.

But for some reason, I just cannot read or write on the SPI bus....