Stack Push Control for ISR

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Stack Push Control for ISR

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by JoshSherman on Tue Jul 12 10:56:48 MST 2011
I am currently writing a time dependent routine wherein my code is watching a 32 bit timer capture input and measuring pulse values up to 500KHz. Everything works properly at  48MHz processor speed but this is a little higher than the desired clock speed for the application. I have optimized my capture interrupt so that it takes very little time, but I can see that my stack pointer changes by a value of 28 from my main loop to the interrupt routine and back. My interrupt certainly doesn't need all of those values pushed onto the stack just so they can be popped back off when my tiny interrupt is over. How can I control what is put onto the stack (and what is not) when my ISR is activated by my capture input?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by JoshSherman on Tue Jul 19 13:12:46 MST 2011
I have highly manually optimized the routine by using assembly code as well as removing as much of the legwork from the ISR as possible. I guess I will need to compile with optimization and stop debugging at this point, and have a serial line spit out my results so I can see how slow the clock can move and still get the job done. Thanks guys.
~Josh
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by NXP_USA on Tue Jul 12 15:36:32 MST 2011
Turning on optimization should have a positive impact on the code. It may be worth looking at the disassembly to see if anything you're doing in C could be simplified. Also- you didn't mention which part you're using, but the interrupt latency is a little less on M3 v.s. M0. Also make sure your interrupt does not call any functions. Usually calling a function will cause the compiler to save more registers than if you don't call one.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by JoshSherman on Tue Jul 12 11:52:41 MST 2011
I was thinking that might be the case. I guess a better question to ask would be: is this something that is going to get better when I do a release build and turn on full optimization? Based on my calculations, I shouldn't have to run at 48MHz to make this work properly.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by gbm on Tue Jul 12 11:39:13 MST 2011
Simple: design a processor by yourself. Cortex M pushes 4 g.p. registers plus some others automatically in hardware.
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