Who is writing User Manual 10524?

[lpcware]

Content originally posted in LPCWare by R2D2 on Tue Jul 02 03:52:01 MST 2013
NXP, your 'UM10524 Rev. 4 — 12 March 2013' writer is a shame. Where's Chapter 6?

2 pages 'Chapter 6: LPC1315/16/17/45/46/47 NVIC'  and then:

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Quote:

6.5 Register description
[COLOR=Red]See the ARM Cortex-M3 technical reference manual[/COLOR]

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[lpcware]

Content originally posted in LPCWare by R2D2 on Wed Jul 03 05:45:43 MST 2013

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Quote: cfb
I usually find that the primary source of information of this sort is the most reliable. As soon as it is copied / pasted to somewhere and 'improved' or paraphrased instead of simply being referenced, errors are likely to creep in.

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To come back to Chapter 6-NVIC: Do you really think that a simple interrupt register description shouldn't be part of UM?

I'm not talking about tail-chaining. Just the basic registers. Like table 67 in old LPC13 UM10375:

Table 67. Register overview: NVIC (base address 0xE000 E000)
Name Access Address offset Description Reset value
ISER0 RW 0x100 Interrupt Set-Enable Register 0. This register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions.

ISER1 RW 0x104 Interrupt Set-Enable Register 1. This register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions.

ICER0 RW 0x180 Interrupt Clear-Enable Register 0. This register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions.

[lpcware]

Content originally posted in LPCWare by cfb on Wed Jul 03 05:33:53 MST 2013
I usually find that the primary source of information of this sort is the most reliable. As soon as it is copied / pasted to somewhere and 'improved' or paraphrased instead of simply being referenced, errors are likely to creep in.

In the case of core Cortex-M3 features that have been implemented faithfully in  an NXP microcontroller a direct reference to the ARM documentation leads me to believe that it is a standard implementation and I don't then have to compare the two sources to discover what the differences are.

If the two are similar but different I would prefer just to see the list of differences in the secondary source.

[lpcware]

Content originally posted in LPCWare by R2D2 on Wed Jul 03 05:21:34 MST 2013
So do you think a list of signatures with famous names is necessary?

Or the usual NXP survey to figure out who is reading this manual or trying to work with it?

And something to win in this campaign would be a good idea. Maybe a good old 8051 manual :)

[lpcware]

Content originally posted in LPCWare by cfb on Wed Jul 03 05:02:37 MST 2013

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Quote: R2D2
perhaps someone responsible is interested in what customers think about this new manual style.

If you feel offended or flamed, flame back. I'm old enough. Or just use 'Ignore List'. This is a forum, and from my point of view this is a discussion...

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From this discussion so far they would conclude that 66.6% prefer the style that doesn't duplicate material from other sources and 33.3% don't.  ;)

[lpcware]

Content originally posted in LPCWare by R2D2 on Wed Jul 03 02:09:23 MST 2013
Sorry for the misunderstanding. This thread in not about 'Don't know Google, can't find Datasheet...'

The question is: [B]Who is writing User Manual 10524?[/B]

Are you writing this manual? If fear this discussion is wasted time again, but perhaps someone responsible is interested in what customers think about this new manual style.

If you feel offended or flamed, flame back. I'm old enough. Or just use 'Ignore List'. This is a forum, and from my point of view this is a discussion...

[lpcware]

Content originally posted in LPCWare by Rob65 on Wed Jul 03 00:15:36 MST 2013
on the risk of being shot again ...

Calling the split up in different documents nonsense or stupid and flaming us for showing you where to find your information is not going to help you.

[lpcware]

Content originally posted in LPCWare by R2D2 on Tue Jul 02 07:00:45 MST 2013

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Quote: cfb
Where would you stop? UM10360 has 82 pages spelling out  the Cortex-M3 instruction set. Would you like to see that repeated in  every NXP Cortex-M3 manual as well?

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And I like them. Unfortunately there are no cycle counts included as in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/CHDDIGAC.html

Chapter 34 is including a lot of useful informations. A search for 'pipeline' in UM10524 just gives me 1 result in introduction :confused:

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Quote: cfb
Would you like to see that repeated in  every NXP Cortex-M3 manual as well?

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Yes, why not. Any questions? So RTFM of the chip. That's a good procedure, isn't it?

[lpcware]

Content originally posted in LPCWare by cfb on Tue Jul 02 06:34:50 MST 2013

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Quote: R2D2
UM10360 is just including this important registers in Chapter 6. Is that so difficult?

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Where would you stop? UM10360 has 82 pages spelling out the Cortex-M3 instruction set. Would you like to see that repeated in every NXP Cortex-M3 manual as well?

[lpcware]

Content originally posted in LPCWare by R2D2 on Tue Jul 02 06:26:01 MST 2013

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Quote: cfb
If you are developing for these microcontrollers a copy of the ARM Cortex-M3 Technical Reference Manual is an essential item in your library so what would be the point of regurgitating the material in the NXP documentation as well?

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Yes, it's my daily business to migrate from LPC11 to LPC13 or LPC17 or Atmel...

Therefore it's useful to include important registers in 1 document. That's not impossible, like other UMs are showing us.

And to open an ARM manual to check a simple priority register is just ridiculous. No package information, no registers. To use this chip I need UM, Datasheet and ARM Reference? Come on, that's nonsense. Just add that parts in a new Rev.

[lpcware]

Content originally posted in LPCWare by R2D2 on Tue Jul 02 06:14:08 MST 2013
@ROB65

If an UM doesn't even mention simple registers like Interrupt Priority registers, that's nonsense. And I don't care if you are trying to defend this nonsense again.

Obviously you are not working with this manual. UM10360 is just including this important registers in Chapter 6. Is that so difficult?

[lpcware]

Content originally posted in LPCWare by Rob65 on Tue Jul 02 05:52:57 MST 2013
This R2 unit has a memory problem.
In another topic from R2D2 I already wrote:

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Quote:
Yes - when you need to go "all the way" and need the details about  interrupt handing or ARM Cortex specific registers you need to consult  the ARM Cortex manuals and if you want to know exactly how the assembly  instructions behave you need the ARM Cortex programmers model also

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Interrupt handling was one of the issues that I specifically mentioned as stuff that you have to consult the ARM Cortex manuals on :eek:

There is absolutely no need to recreate the same information from elsewhere.

Rob

[lpcware]

Content originally posted in LPCWare by cfb on Tue Jul 02 05:17:16 MST 2013
If you are developing for these microcontrollers a copy of the ARM Cortex-M3 Technical Reference Manual is an essential item in your library so what would be the point of regurgitating the material in the NXP documentation as well?

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