LPC812 UART Baud Rate Issue (faster than expected)

[lpcware]

Content originally posted in LPCWare by mvinger on Sat Jun 22 20:14:34 MST 2013
I found a weirdness and searched all the docs to discover what my error might be. I used a board to board UART channel setup at 115200 and all seemed to work fine. I then went to hook-up a separate UART receiver-only for some simple IR remote stuff (someone else's remote). It only sends two bytes in N81 at 300 bps. The RX-only channel would not work. Then I noticed an elongated data pattern from what I got to what was sent.
I hooked up the logic analyzer and verified the 300bps on the RX-only channel and the data was as expected. I then halved the baudrate setting sent to initialize the channel and wala (however you spell it), I could read the data appropriately.
I then checked my 115200bps full-duplex UART channel and it was running at 250kbps.
Anyone have a clue as to if there is an error in the docs or am I missing something else.
The LPC812 is configured to run at the max 30MHz from the internal osc as the base. The UART div is set to 1 so the PLL clock should match the 30MHz system clock.

Perplexed!

MTV2

[lpcware]

Content originally posted in LPCWare by vijay_nav on Thu Dec 26 22:57:45 MST 2013
Hai
      I am working on LPC-812 board and i had worked with some example in the lpcxpresso tool.while working with the blinky example it works fine but i need fading in and fading out led for the blinky.I am not able to do that can any help me how to do that fading in and fading out the led.

[lpcware]

Content originally posted in LPCWare by mvinger on Sun Jun 23 10:28:15 MST 2013
Ah!
Thank you.
I missed that.
Assumptions and semantics can be a killer.
Your help has been much appreciated.
This means that the LPC800_driver_lib has made incorrect assumptions.
I will make notes and corrections.
Take care.

MTV2

[lpcware]

Content originally posted in LPCWare by noahk on Sun Jun 23 10:22:04 MST 2013
Hi MTV2,

I think I see the problem. The SYSAHBCLKDIV drives the system clock, but the FRG gets the clock from the main clock. The main clock is 60 mhz. The system clock is 30 mhz.

What you are getting is
60000000 / (1 + 4/256) = 59076923
59076923 / 16 = 3692307
3692307 / 16 = 230769

Noah

[lpcware]

Content originally posted in LPCWare by mvinger on Sun Jun 23 09:58:30 MST 2013
Hello Noah.
Thanks for the reply.

I am using the lp800_driver_lib and the CMSIS_CORE_LPC8xx.

SystemInit is initializing the PLL using the 12MHz IRC as an input and MSEL = 4 (M=5) and PSEL = 1 (P=2) which produces a 12MHz * 5*(2*2) = 240MHz FCCO clock and the PLL output clock is 240MHz/(2*2) = 60MHz.
The SYSAHBCLKDIV register is set to 2. Thus the system clock is 60MHz/2 = 30MHz. The SystemCoreClockUpdate confirms this with SystemCoreClock = 60,000,000.

UARTInit/UARTClock_Init set UARTCLKDIV to 1 and UARTSysClk is calculated at 30,000,000.
BRG is then set at 15 (divide UARTSysClk by 16).
UARTFRGMULT is then set for 4.
The UARTInit function does not get as close to 115200 as you have (I may tweak it now that I see its inefficiency) but it gets to 115384.

Still, all of my input and output baudrates are actually doubled.

MTV2

[lpcware]

Content originally posted in LPCWare by noahk on Sat Jun 22 23:49:41 MST 2013
Hi MTV2,

How are you configuring UARTCLKDIV? UARTFRGDIV/MULT? and BRG? If you are configuring the PLL to drive in 30 MHz, and you are using a UARTCLKDIV of 1. These values should provide you with a 115200 baud rate.

Assuming 30 MHz into the FRG.

UARTFRGDIV=255 (+1=256)
UARTFRGMULT=91
BRG=11 (+1=12)

30000000 / (1 + 91/256) = 22132564 (See section 4.6.18 USART fractional generator divider value register)
22132564 / 12 = 1844380 (Divide by BRG)
1843575 / 16 = 115273 (Divide by oversample rate)

Noah