/* Power Up the EMAC controller. */ LPC_SC->PCONP |= (0x1<<30); LPC_PINCON->PINSEL2 = 0x50150105; #if MDC_MDIO_WORKAROUND /* LPC175x devices, use software MII management. */ LPC_PINCON->PINSEL4 &= ~0x000F0000; LPC_GPIO2->FIODIR |= MDC; #else LPC_PINCON->PINSEL3 &= ~0x0000000F; LPC_PINCON->PINSEL3 |= 0x00000005; #endif /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; /* A short delay after reset. */ for (tout = 100; tout; tout--); /* Initialize MAC control registers. */ LPC_EMAC->MAC1 = MAC1_PASS_ALL; LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; LPC_EMAC->MAXF = ETH_MAX_FLEN; LPC_EMAC->CLRT = CLRT_DEF; LPC_EMAC->IPGR = IPGR_DEF; /* Enable Reduced MII interface. */ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Reset Reduced MII Logic. */ LPC_EMAC->SUPP = SUPP_RES_RMII; for (tout = 100; tout; tout--); LPC_EMAC->SUPP = 0; /* Put the DP83848C in reset mode */ write_PHY (PHY_REG_BMCR, 0x8000); /* Wait for hardware reset to end. */ for (tout = 0; tout < 0x100000; tout++) { regv = read_PHY (PHY_REG_BMCR); if (!(regv & 0x8000)) { /* Reset complete */ break; } } /* Check if this is a DP83848C PHY. */ id1 = read_PHY (PHY_REG_IDR1); id2 = read_PHY (PHY_REG_IDR2); if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) { /* Configure the PHY device */ /* Use autonegotiation about the link speed. */ write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); /* Wait to complete Auto_Negotiation. */ for (tout = 0; tout < 0x100000; tout++) { regv = read_PHY (PHY_REG_BMSR); if (regv & 0x0020) { /* Autonegotiation Complete. */ break; } } } /* Check the link status. */ for (tout = 0; tout < 0x10000; tout++) { regv = read_PHY (PHY_REG_STS); if (regv & 0x0001) { /* Link is on. */ break; } } /* Configure Full/Half Duplex mode. */ if (regv & 0x0004) { /* Full duplex is enabled. */ LPC_EMAC->MAC2 |= MAC2_FULL_DUP; LPC_EMAC->Command |= CR_FULL_DUP; LPC_EMAC->IPGT = IPGT_FULL_DUP; } else { /* Half duplex mode. */ LPC_EMAC->IPGT = IPGT_HALF_DUP; } /* Configure 100MBit/10MBit mode. */ if (regv & 0x0002) { /* 10MBit mode. */ LPC_EMAC->SUPP = 0; } else { /* 100MBit mode. */ LPC_EMAC->SUPP = SUPP_SPEED; } /* Set the Ethernet MAC Address registers */ LPC_EMAC->SA0 = (MYMAC_6 << 8) | MYMAC_5; LPC_EMAC->SA1 = (MYMAC_4 << 8) | MYMAC_3; LPC_EMAC->SA2 = (MYMAC_2 << 8) | MYMAC_1; /* Initialize Tx and Rx DMA Descriptors */ rx_descr_init (); tx_descr_init (); /* Receive Broadcast and Perfect Match Packets */ LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; /* Enable EMAC interrupts. */ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Reset all interrupts */ LPC_EMAC->IntClear = 0xFFFF; /* Enable receive and transmit mode of MAC Ethernet core */ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); LPC_EMAC->MAC1 |= MAC1_REC_EN; |
void Init_EthMAC(void) { unsigned int value; volatile unsigned int loop; // Set Ethernet power/clock control bit LPC_SC->PCONP |= PCENET; //Enable Ethernet pins through PINSEL registers LPC_PINCON->PINSEL2 = ENET_PINSEL2_CONFIG; LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~(ENET_PINSEL3_MASK)) | ENET_PINSEL3_CONFIG; // Set up MAC Configuration Register 1 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |MAC1_SIM_RES | MAC1_SOFT_RES; // Set up MAC Command Register LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; // Short delay for (loop = 100; loop; loop--); // Set up MAC Configuration Register 1 to pass all receive frames LPC_EMAC->MAC1 = 0;// MAC1_PASS_ALL; // Set up MAC Configuration Register 2 to append CRC and pad out frames LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; // Set Ethernet Maximum Frame Register LPC_EMAC->MAXF = ETH_MAX_FLEN; // Set Collision Window / Retry Register LPC_EMAC->CLRT = CLRT_DEF; // Set Non Back-to-Back Inter-Packet-Gap Register LPC_EMAC->IPGR = IPGR_DEF; /* Enable Reduced MII interface. */ LPC_EMAC->MCFG = MCFG_CLK_DIV64 | MCFG_RES_MII; for (loop = 100; loop; loop--); LPC_EMAC->MCFG = MCFG_CLK_DIV64; // Set MAC Command Register to enable Reduced MII interface // and prevent runt frames being filtered out LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;// | CR_PASS_RX_FILT; // Put DP83848C PHY into reset mode WriteToPHY (PHY_REG_BMCR, 0x8000); // Loop until hardware reset completes for (loop = 0; loop < 0x100000; loop++) { value = ReadFromPHY (PHY_REG_BMCR); if (!(value & 0x8000)) { // Reset has completed break; } } [COLOR=Red] WriteToPHY (PHY_REG_BMCR, 1<<11); //power down[/COLOR] } |
WriteToPHY (PHY_REG_BMCR, 1<<11); //power down and save >40mA |
WriteToPHY (PHY_REG_BMCR, 1<<11); //power down and save >40mA |