M4 & M0 cores communication via SDRAM or IPC

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by maszup on Sat Apr 13 15:18:14 MST 2013
I'm begginer using LPC4357 with lpcxpresso and dual core. i have made both axf files and upladed them to both cores flash.

I'm trying to synchronize both cores in my software.

First i decided to try using SDRAM. M4 is reading first 4bytes of SDRAM and M0 is writing to that bytes but M4 goes immediately to Hard Fault. I don't know if it is possible to read & write SDRAM with two cores in the same time?


uint32_t *temp = (uint32_t*)SDRAM_BASE;

while(1) {

sprintf(buff, "value = %d\r\n", temp[0]);





uint32_t *temp = (uint32_t*)SDRAM_BASE;

uint32_t idx =0;

while(1) {

  temp[0] = idx++%100000;


but on cosole i get some rubbish like "<0><0><0><0><0><0><0><0><0><0><0><0><0><0><0><0>" and console stops, probably M4 goes to hard fault . WHat is going on here?

Then i thought of using IPC but i do not have examples under LPCxpresso only under Keil. The example of IPC is nice but it is using M0 image read from CM0_image.c file  and M4 is uploading this image to M0. I do not know how to generate such a file in LPCxpresso. The examples is here: