Content originally posted in LPCWare by igorsk on Thu Jan 21 16:02:40 MST 2010
As SysTick is (supposed to be) standard to all Cortex-M3 implementations, the registers are also described in the ARMv7-M Architecture Reference Manual (DDI0403 or DDI0405), as well as in Cortex-M3 TRM (DDI0337). The latter descibes the register thus:
[31:17]
Reserved.
[16] COUNTFLAG
Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.
[2] CLKSOURCE
0 = external reference clock.
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable.
[1] TICKINT
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0.
[0] ENABLE
1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.
0 = counter disabled.
