LPC111x clocks

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by rkiryanov on Thu Feb 11 05:05:11 MST 2010
UM (11 January 2010), Fig 3. LPC111x CGU block diagram points that SPI0_PCLK is sourced directly from "main clock". Top right corner of this figure points that "AHB clocks 1 to 18 (memories and peripherals)" (I don't understand, how it can affect if peripherals are connected before this block). In PLC2xxx all peripheral clocks is sourced after CCLK and clocking directly from "main clock" is something new. What is correct?