LPC1343 Examples: SSP CR0 Inconsistency

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by ktownsend on Thu Jan 14 09:31:57 MST 2010
There seems to be an inconsistency in the SSP demo code in the following line:

/* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
LPC_SSP->CR0 = 0x0707;

The comment leads you to believe that SCR is 15, but 0X0707 corresponds to the SCR bits (15:8) being set to 0000 0111 (decimal 7). In any case, I don't seem to be able to get a correct clock signal supplying either 7 or 15 for the SCR bits.

Am I right in the following understanding for the SSP clock if the device is running at 72MHz and SCR is set to 7:

72000000 / (2 [CPSR] x (7 [SCR] + 1)) = 4.5MHz

I seem to be getting inconsistent/irregular clock signals, and have been trying to track down the problem. In any case, you might want to update the comment in any future revision to be less misleading.