Content originally posted in LPCWare by vivien.wong on Sun Mar 20 18:11:23 MST 2016
Hi
I'm reading from the link you gave earlier and it says:
On the LPC-Link2, when JP2 is shunted this will power the target side of the dual-supply buffer and provide power to the target through a diode on VTref. With JP2 open the target must supply the VTref to power the target side of the dual-supply buffer.
When a debug probe attempts to adjust logic levels based on the voltage it sees on VTref, this is referenced to whatever GND it has to work with. The voltage at VTref is coming from your target, thus you need a good GND, shared with your target hardware.
So it is possible that with JP2 open, the target is providing supply to VTref. Could you point out exactly which signal is VtRef on the LPC-Link2? What should the VTRef level be for a debuggable condition?
Thanks!