Failed on connect. Target marked as not debuggable

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Failed on connect. Target marked as not debuggable

480 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vivien.wong on Thu Mar 17 23:11:34 MST 2016
Hi,

   I am using a LPC1857 and I am not able to connect to the LPC-Link2 or Red Probe debugger. This is what I've tried out:

1. I am able to enter ISP mode and I erased the entire flash bank A and bank B and then I tried to debug but still to no avail. This rules out that the firmware is problematic since even on a completely erased part, I cannot enter debug mode.
2. CRP is definitely disabled.
3. I enabled "Vector Catch" in debugger option and that didn't work too.

  Since firmware code is likely not the culprit, could anyone give me pointers on what part of the hardware I should be checking to ensure that I can get to debug to work? I read that Vtref between target and debugger hardware have to match. How do I check and ensure this is the case?


Thank you!

Vivien
0 Kudos
6 Replies

459 Views
lpcware
NXP Employee
NXP Employee
bump
0 Kudos

459 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vivien.wong on Sun Mar 20 18:22:27 MST 2016
By the way, is there a way to provide a delay before the debugger tries to connect? Is it an option that I can set in the debugger?
0 Kudos

459 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vivien.wong on Sun Mar 20 18:11:23 MST 2016
Hi

  I'm reading from the link you gave earlier and it says:

On the LPC-Link2, when JP2 is shunted this will power the target side of the dual-supply buffer and provide power to the target through a diode on VTref.  With JP2 open the target must supply the VTref to power the target side of the dual-supply buffer.

When a debug probe attempts to adjust logic levels based on the voltage it sees on VTref, this is referenced to whatever GND it has to work with. The voltage at VTref is coming from your target, thus you need a good GND, shared with your target hardware.

  So it is possible that with JP2 open, the target is providing supply to VTref. Could you point out exactly which signal is VtRef on the LPC-Link2? What should the VTRef level be for a debuggable condition?

Thanks!
0 Kudos

459 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vtw.433e on Sun Mar 20 15:45:15 MST 2016

Quote:
so my board is providing power to the LPC Link2


Err, that is not possible! Lpc-link2 can provide power to your board, but not the other way round. You should NOT try to provide power to link2.

My guess is you have power problems
0 Kudos

459 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vivien.wong on Sun Mar 20 15:27:39 MST 2016
Yes, I've read that a few times. I have a few boards with similar design, some work (debuggable) and some don't. I have JP2 un-shunted on the LPC Link2 so my board is providing power to the LPC Link2. I tried to shunt JP2 but it doesn't work either.
0 Kudos

459 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by vtw.433e on Fri Mar 18 09:15:20 MST 2016
Did you read this?
https://www.lpcware.com/content/faq/lpcxpresso/debug-design
0 Kudos