I2C Timing Problem

[lpcware]

Content originally posted in LPCWare by rfdesign on Thu May 24 11:27:05 MST 2012
Hi,
we are using the i2c sample code from "CMISSV2_LPC17xx" code boundle. When writing to an EEPROM located at address AE we are getting no correct I2C address and data values on the bus, please see attached Logic-Analyser Screen.
The problem seems to be the clock SCL, the first periode comes too early and the start condition seems to be very short. The I2C interpreter says that it is address 57h instead of AEh, also the following data bytes are shifted by one bit to the right.....
FYI: We use LPC1769 XPresso Board
Anyone an idea?
Regads,
Ralf

[lpcware]

Content originally posted in LPCWare by researchinnovation on Mon May 28 22:09:21 MST 2012

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Quote: rfdesign
Hi,
we are using the i2c sample code from "CMISSV2_LPC17xx" code boundle. When writing to an EEPROM located at address AE we are getting no correct I2C address and data values on the bus, please see attached Logic-Analyser Screen.
The problem seems to be the clock SCL, the first periode comes too early and the start condition seems to be very short. The I2C interpreter says that it is address 57h instead of AEh, also the following data bytes are shifted by one bit to the right.....
FYI: We use LPC1769 XPresso Board
Anyone an idea?
Regads,
Ralf

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Hi... !!!

Is it coming correctly.

Thanks & Regards....:)

[lpcware]

Content originally posted in LPCWare by Rob65 on Sun May 27 00:12:50 MST 2012

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Quote: rfdesign
My I2C Bus is about 50cm long in total, the Pull-Ups are close to the IO Ports of the LPC Board, so the effect is that we get reflections at the end of the "open" bus

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That should be easy to find for a user called RFdesign ;)

I've just looked at your logic analyzer output and there are some strange things that should trigger you:
1) The clock is not a 50% duty cycle clock. Normally the I2C clock is programmed to have a nice 50% duty cycle.
2) There are some strange spikes on your SDA line (on a H-L edge on SCL)  that should really not be there. This can be due to your bus terminations but it can also be due to wrong settings in the logic analyzer.
3) The analyzer does not show the start condition. After detecting the start condition you should see something like "W:57" to show it's writing to your slave.
4) You are using a LogicPort from Intronix, I have the same one and it works OK as long as you do keep in mind its limitations. The signals are fed directly to an FPGA, there is no signal conditioning or high end input stage like you'll find in expensive analyzers. This might also influence your signals (especially when not properly terminated). High impedance signals should not be fed directly into the LogicPort. Just for fun: connect the analyzer to a high impedance signal (i.e. an unused input to your processor) and measure what that signal does (oscilloscope/voltmeter) when you change the logic threshold setting.

You could have a look at the analyzer picture on [U]this page[/U], it shows a complete transaction as I captured it with my own I2C driver (on the same page).

Yes - I know, you fixed your problem. But it could never hurt to have a look at some other reference material :)

Rob

[lpcware]

Content originally posted in LPCWare by rfdesign on Fri May 25 06:31:29 MST 2012
Hi guys,
thanks for replying!
I found the problem: My I2C Bus is about 50cm long in total, the Pull-Ups are close to the IO Ports of the LPC Board, so the effect is that we get reflections at the end of the "open" bus, which results in phaseshifting effects of both lines. So placing the pull-ups at the end of the bus and inserting some "small" (100Ohm) serial resistors in the lines close to the board makes the bus working correct.
Regards,
Ralf

[lpcware]

Content originally posted in LPCWare by researchinnovation on Thu May 24 22:33:27 MST 2012
@Rfdesign...Hi..!!!

For cross checking please try once with an Oscilloscope.
I had tried I2C with an oscilloscope for LPC1114/301, I was getting it correctly.
Logical analyzer I found bit complex in handling.


Thanks & Regards.....:)

[lpcware]

Content originally posted in LPCWare by atomicdog on Thu May 24 20:28:34 MST 2012
What value of the required pullup resisters do you have?

The screen shot is of a [U]read[/U] to address 56h with an acknowledge.
So there is a device at the 7-bit address 56h (ACh / ADh) that is acknowledging.
It's not a [U]write[/U] to...

It may be that the Logic-Analyzer is misinterpreting it though.
You can try slowing down the clock and re-testing.