SPI - Interrupt of TxFIFo half empty

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Deepak Bansal on Thu Oct 04 04:51:27 MST 2012

I have to use SPI mode to transmit 100 bytes on a line as fast it can be.
Data received is don't care.

So I am using this interrupt. Now have some questions regarding this:

1. What is size of Tx FIFO. Is it the no of bit transfer which we select. like for 8 bit transfer, TxFIF0 is 1 byte long?????

2. Also, when received interrupt of TxFIF0 half empty, when to load next byte in data register again & after what time ????????
Again data received is don't care.