LPC1115, SSP registers not setting

[lpcware]

Content originally posted in LPCWare by johnnyfp on Mon Oct 13 23:20:48 MST 2014
Hi,

I'm trying to setup the SSP on my LPC1115Dev board and for the life of me I can't get the registers to set.

In eclipse I step through in debug mode, and can see the statements executing but the registers just don't update and if I read them back I always get zero. I even print the register, thinking that maybe the debug if not working properly.

LPC_SSP0->CR1=0xC;
LPC_SSP0->CR1=0xE;
printf("0x%x\n",LPC_SSP0->CR1);

I've made sure that the SPI and IOCON clocks are on and have set the SPI clock to be /4 of the IRC PLL of 48Mhz just incase its a clock issue, with still no luck.

Can anyone give me any pointers please.

Cheers

Original Attachment has been moved to: workspace2.zip

[lpcware]

Content originally posted in LPCWare by johnnyfp on Tue Oct 14 02:44:05 MST 2014
Thank you, That did the trick, I missed that step of the SSP needing the reset switch off. And yes there is a LPCOpen sample, but I find them a little confusing. Need to re visit them, specially if I'm trying to get the LPC to be a slave and I'm not so tired.

Cheers

[lpcware]

Content originally posted in LPCWare by LabRat on Mon Oct 13 23:56:36 MST 2014
Isn't there a LPCOpen sample  :quest:

Try:

LPC_SYSCON->PRESETCTRL &= ~(1 << 0);
LPC_SYSCON->PRESETCTRL |= (1 << 0);
SSP_Init(0);

UM:

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Quote:

14.2 Basic configuration
The SPI0/1 are configured using the following registers:
1. Pins: The SPI pins must be configured in the IOCONFIG register block. In addition,
use the IOCON_LOC register (see Section 7.4) to select a location for the SCK0
function.
2. Power: In the SYSAHBCLKCTRL register, set bit 11 and bit 18 (Table 21).
3. Peripheral clock: Enable the SPI0/1 peripheral clock by writing to the SSP0/1CLKDIV
registers (Section 3.5.15 and Section 3.5.17).
4. [color=#f00]Reset: Before accessing the SPI blocks, ensure that the SSP_RST_N bits (bit 0 and
bit 2) in the PRESETCTRL register (Table 9) is set to 1. This de-asserts the reset
signal to the SPI blocks.[/color]

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