Problems with Power modes

[lpcware]

Content originally posted in LPCWare by robert.palmer on Wed Oct 10 14:01:02 MST 2012
I'm using an LPC1756 and working with SLEEP mode and PowerDown mode.  I finally got it running, but still have some questions/issues.

I am currently disabling the PLL before PowerDown() mode and then re-enabling after wakeup().
I am using a GPIO2 pin to trigger the wake up.  All my ISR does is clear the interrupt

In the CMSIS2.0 lib from NXP the CLKPWR_Sleep()
[LIST]
- sets ONLY the LPC_SC->PCON
[INDENT] -- it does NOT CLEAR the DEEPSLEEP bit.  This means if you use a CLKPWR_PowerDown()
         and then the next time, you call CLKPWR_Sleep() you'll actually drop into DeepSleep().
        Was this an oversight or is there a specific reason it's not cleared inside this helper function?
[/INDENT]
- sets ALL bits in the LPC_SC->PCON register not just the sleep mode bits
[INDENT]   -- this includes ENABLING the BOD flags, while the DeepSleep() and PowerDown() explicitly
        DISABLE the BODG.  Why?
[/INDENT]
[/LIST]
I looked at this thread: http://knowledgebase.nxp.com/showthread.php?t=2071

He had an issue with BOD getting set and then the chip resets, but I saw no resolution.  I'm have the same issue.  if I modify the CLKPWR_Sleep() to ONLY clear the sleep mode bits (b0, b1) and keep the BODG disabled, my code works.  However, if I use the NXP original code (LPC_SC->PCON = 0x00) as
soon as I execute this, my processor resets and the BOD flag gets set.

I thought maybe it was a lingering flag, so I made sure I cleared the BOD flag before calling CLKPWR_Sleep() this didn't help.  If I turn on the BODG (clear the bit) then I get a reset.  Is this some errata related to sleep modes? 

I have used a scope to verify that my Vdd is NOT dropping.  I'm running at 3.0V and the lowest I see it go is about 2.9V, but no where near the 2.2V to trigger BOD and the time when it does drop is AFTER the reset, during startup, not BEFORE the reset where I would expect to see it if it were actually triggering the BOD reset.

Summary:

- Why does CLKPWR_Sleep() not clear the DEEPSLEEP bit?
- Why am I seeing a BOD reset when I call CLKPWR_Sleep(), specifically at the point when I set the LPC_SC->PCON register to 0x00, BEFORE the WFI instruction.

[lpcware]

Content originally posted in LPCWare by robert.palmer on Mon Oct 15 08:45:03 MST 2012
Ok, MAYBE this is a contributing factor:

I was just reading through the Errata and came across #3.14 for the LPC175x series.  It says the device [B]does not work[/B] when the regulator supply voltage is lower than 3.0V. 

I'm using 3.0V regulators as input to my device, so ANY drop in voltage could cause a problem.  It's not clear if this errata is an "it definitely will not work" or a "NXP cannot guarantee functionality" (similar to over clocking, it might or it might not work).  In my case, it generally seems to work at 3.0V, but maybe there is some case around Sleep that causes problems when the supply is at 3.0V.  I need to test with 3.1 or higher.

[lpcware]

Content originally posted in LPCWare by robert.palmer on Mon Oct 15 07:42:15 MST 2012
Yes, I have seen that App Note.  However, I have not tried running the code on a demo board. 

Yes, clearing the SLEEPDEEP bit after waking up (this applies to DeepSleep, PowerDown AND DeepPowerDown) would be a reasonable alternative, but I think making sure it is clear before attempting sleep is also necessary - the function call wrapper is called CLKPWR_Sleep(),  symantically, this should ensure that ONLY Sleep mode is entered, which means it should ensure that the SLEEPDEEP bit is not set.

Yes, I thought about the BORD bit in the RSID being the problem, therefore, immediately before the CLKPWR_Sleep(), I have a test to see if the BODR bit is set and if it IS set, I do two things:
1. clear it
2. generate a debug trace so I can see if it is ever set at this point.

I also test the BORD bit immediately after waking from PowerDown (or DeepSleep depending on the mode I'm testing) and it is NOT set after waking from PowerDown (or DeepSleep).

It makes no sense why I am getting a Brown-Out reset, but it also appears that I'm not the only one that's run into this issue.

Why is the default for DeepSleep and PowerDown to SET the BOGD (disabling the Brown-Out reset)?

Based on my testing, the BODR bit in the RSID reg is never ON.

[lpcware]

Content originally posted in LPCWare by daniel.widyanto on Mon Oct 15 00:52:24 MST 2012
Hello,

Have you seen this ? AN10915 Using the LPC1700 power modes (http://www.nxp.com/documents/software/AN10915.zip) :)

For 'CLKPWR_DeepSleep()', I believe it should clear the SLEEPDEEP bit after waking up. I'll pass it to the team who develops this.

For BOD reset if BORD in PCON activated before going to deep sleep,could you check if BODR in RSID (Reset ID reg) is ON ?

[lpcware]

Content originally posted in LPCWare by robert.palmer on Wed Oct 10 15:15:21 MST 2012
Additional Information: 
I have the SAME issue if I use DeepSleep() or PowerDown().

Also if I modify PowerDown() to NOT DISABLE BOGD - my code will not wake up from the external interrupt.  While with the hacking noted above, I am able to get my code to work.  I really want to understand this interaction/issue with the BOGD setting.  At the moment, I'm not using the Brown-Out detection, but at some point, it may become a necessity.