LPC17xx series, FLASH and PowerDown

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by robert.palmer on Mon Oct 15 07:50:15 MST 2012
According to the data sheet, in the PowerDown mode the FLASH is turned off.  This implies that, upon wake, one cannot execute from FLASH until the FLASH has had a chance to power on.  Is this managed by the hardware?  In other words, IF one attempts to execute from FLASH (e.g. ISR that is executed on wake is running from FLASH) does the FLASH interface insert wait states until the FLASH is ready or is it fully the programmers responsibility to make sure the FLASH is ready?

If it is the programmers responsibility, then I would assume that the ISR should be executing from RAM and should ensure that either the code after the WFI is also executing from RAM or should pause the processing until the FLASH is ready.

This is not at all discussed in any of the documentation I have found.  I have code that runs fully from FLASH and uses the PowerDown mode, but it SEEMS to work fine.  The ISR executes and the code wakes up and continues.  Maybe the issue that a developer must be aware of is the extra ISR delay because of waiting for the FLASH to wake, so if the ISR must respond very quickly, then it should be in RAM.

Is this correct?