Content originally posted in LPCWare by lpc1700user on Fri Nov 08 12:10:55 MST 2013
Thank you for replies.
10K and 22K does not help.
In the mean time I found the 3.3V system voltage drops significantly when LP-link assert the /RESET (not the same think happens with JLINK !), that explains the debugging issues.
On my setup, LPC-link is power by the USB, with no connection to the system 3.3V . The connections resume to: SWDCLK, SWDIO, RESET and GND.
On the custom board there is a "OR" using open drains outputs between ISP bus RESET (OD buffer), SWD RESET (LPC-link reset) and internal POR (ADM1816 - OD output).
I think the issue is on the LPC-link reset output. Is it an Open drain output? (I will try to add an extra OD buffer)
How do you guys power and connect LPC-link to your target?
Thank you.