Understanding the Cortex-M3 (LPC1769) interrupt model.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by skysat on Sat Jan 18 10:33:40 MST 2014
I'm having trouble understanding exactly how interrupts/exceptions work on the M3.  To my way of thinking, an interrupt works like this:

1. Push the PSR (which includes the interrupt enable bit).
2. Push the PC.
3. Disable interrupts.
4. Execute the ISR.

The ISR may or may not re-enable interrupts but upon exit, the former PSR will be restored thus restoring the former interrupt enable/disable state.  The following code is at the end of my ISR:

213       }
0000c0d0:   add.w   r7, r7, #24
0000c0d4:   mov     sp, r7
0000c0d6:   pop     {r7, pc}
0000c0d8:   adds    r5, r7, #4
0000c0da:   asrs    r0, r0, #32

(Are the last two instructions filler or data?  I notice that "Show Opcodes" doesn't do anything.)
The debugger seems to think that I have a PSR (although it doesn't know what the bits mean).   Where is the PSR documented. I don't see any interrupts being enabled.

So, are interrupts globally disabled?  Is the particular interrupt disabled?  Can someone explain EXACTLY what is going on?

You would think that the answer to these questions would be in the "Cortex-M3 Technical Reference Manual" (there is a puny chapter on the NVIC).


An then there is the matter of return address 0xfffffff8.  I'll handle that in my next post - "Where's my stack?".