Content originally posted in LPCWare by UKlakow on Thu Oct 06 08:31:38 MST 2011
Yes I get it what you say, about in the user manual, chapter 4.10.4 table, the 3 line is printed:
[COLOR=Teal][B] FCLKOUT Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz.[/B][/COLOR]
if a config the clock divider's at 2, then the used clocks shut run only 30MHz!
Now I now what is the problem, in the file "sytem_LPC122x.c" what is generated from the LPCXpresso IDE is a wrong configuration sequence. The code line:
[B][COLOR=Teal] LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;[/COLOR][/B]
follow a couple of line later is the line:
[COLOR=Teal][B]LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;[/B][/COLOR]
and the outer settings of the other divider register for the outer lines.
after i move the line in front of:
[B][COLOR=Teal] LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
[/COLOR][/B][COLOR=Teal][COLOR=Black]the MCU run with 30MHz!
The only more question about this fix is this: if a new MCU is startup, is it possible to change the SYSAHBCLKDIV befor
the setting of SYSPLLCTRL register?
[/COLOR][/COLOR] my Question 2) was about the clockout signal: now i have solved this also by my self, for this operation i had been insert two lines in the same file:
[COLOR=Teal][B]#if (CLKOUTCLK_SETUP)
LPC_SYSCON->CLKOUTCLKSEL = CLKOUTCLKSEL_Val;
LPC_SYSCON->CLKOUTDIV = CLKOUTCLKDIV_Val;
LPC_SYSCON->CLKOUTUEN = 0x00;
LPC_SYSCON->CLKOUTUEN = 0x01;
#endif[/B][/COLOR]
now i see 30MHz at the clock output pin!
Best regards from germany, Ulrich Klakow