lpcware

Syspllclkuen/mainclkuen

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by curtvm on Mon Oct 25 10:22:51 MST 2010
I'm trying to square away the datasheet to the code in [I]system_LPC11xx.c[/I]

According to the datasheet, the update enable registers need a low to high toggle on bit0 for the clock selection updates to occur (according to the clock select register description). The update enable register describes needing to write a 0, then a 1 (which of course meets the 0->1 toggle requirement).

The code in [I]system_LPC11xx.c[/I] writes a 1, then 0, then 1, then waits for the register to change to a 1.

I'm trying to figure out why that sequence is used. And why one needs to wait for the register to change to a 1 after writing a 1 (how long can it take?)

Like I said, just trying to square things up.

(edited- I was reading the code wrong where it is waiting for the register change to 1)

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