MCF5445X: pin assignment for DDR2

[pdrecker]

Hello,

it's the first time that I use a sdram. I decide to take a single chip solution (DDR2 SDRAM 84-Ball, 8 M words x 16 bits x 4 banks).

My planned pin assignment for the 16-bit data bus:

SD_DATA[31] to DQ15 of DDR2 SDRAM
SD_DATA[30] to DQ14 of DDR2 SDRAM
SD_DATA[26] to DQ13 of DDR2 SDRAM
...
SD_DATA[17] to DQ1 of DDR2 SDRAM
SD_DATA[16] to DQ0 of DDR2 SDRAM

The pin assignment for the most signals is clear. But I am unsure with the following signals:

a) Connect SD_DQM3 for SD_D[31:24] to UDM of the DDR2 SDRAM?
b) Connect SD_DQM2 for SD_D[23:16] to LDM of the DDR2 SDRAM?
c) Connect SD_DQS3 for SD_D[31:24] to UDQS of the DDR2 SDRAM?
d) Connect SD_DQS2 for SD_D[32:16] to LDQS of the DDR2 SDRAM?
e) What to do with the signals /UDQS and /LDQS? Left floating?

Looking at the schematics of the M54455EVB I realize that the pin assignment of each 'data bus byte' is in the reverse order.

upper byte
-----
SD_DATA[31] to DQ8 of DDR2 SDRAM
SD_DATA[30] to DQ9 of DDR2 SDRAM
...
SD_DATA[25] to DQ14 of DDR2 SDRAM
SD_DATA[24] to DQ15 of DDR2 SDRAM

lower byte
-----
SD_DATA[23] to DQ0 of DDR2 SDRAM
SD_DATA[22] to DQ1 of DDR2 SDRAM
...
SD_DATA[17] to DQ6 of DDR2 SDRAM
SD_DATA[16] to DQ7 of DDR2 SDRAM

Is there a special reason?

Regards,
Pascal

[JWW]

Pascal,

The secret with SDRAM, DDR, DDR2 is to make sure each data byte lane is matched up with its control signal.

The bit significance within a byte lane does not matter, and can be routed to match the efficiencies of your layout. Of course it is always better to pick some sequential manner. The biggest mistake you could make is to route data lines across control boundaries. In DDR and DDR2 you have DM (data masks) and DQS (data strobes). And they are assigned in both the processor and the memory to specific data lines.

Example:

DQ[31:24] normally is DQS[3]
DQ[23:16] would be DQS[2]
ETC. ETC...

The memories will often refer to the DQS signals as UDQS or LDQS. For upper byte or lower byte...strobes.

Also, you asked about the /LDQS signals. In DDR2 you can use differential DQS signals. The 5445x family does not need differential DQS, as 133Mhz clock does not really justify the extra signals. This is typically used on systems that need 200Mhz clock and 400Mhz data or faster. So these signals are not used on the SDRAMs. If you look at the data sheet for a DDR2 RAM, you'll see that there is a LOAD MODE register command that you have to run to enable the inverted DQS outputs from the RAM.

If you haven't already read the application note we have, it may be a good idea. And we are always open to feedback if you would like to see more info in the current application note or if you need another version that answers different questions.

Lastly.. DDR and DDR2 are not that hard to do.

Weblink:

http://www.freescale.com/files/32bit/doc/app_note/AN3522.pdf?fpsp=1&WT_TYPE=Application%20Notes&WT_V...

-JWW

[w_wegner]

Hi,

I can not comment on the control line assignment in general because I did not yet use the MCF5445x, but as for the data lines, there is no special mapping necessary for DDR memory. Configuration is done through the address lines, but you are free to use a mapping on the data lines such that it best fits your routing space - and I guess this is what Freescale people did on the evaluation board.

Regards,
Wolfgang