lpcware

Nested Critical Sections

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by celephicus on Wed Mar 21 22:29:45 MST 2012
Greetings,

I am just starting out on ARM development with M0 parts, so bear with me.

Working with other processors, if I had a function that can be called from ISR's and from mainline code that accesses some shared resource, I would have some macros to take care of disabling/enabling interrupts. The enterCritical() function saves the existing state on entry, and the leaveCritical() restores it on exit.

int state;
enterCritical(state);
...
leaveCritical(state);

With the wonderful NVIC in the Cortex M0, it seems to me that I can simple use __disable_irq();
...
__enable_irq()

Since the ARM does not disable interrupts during an interrupt. And I just make sure that I do not nest calls to my critical sections (or I could use a counter).

Thanks in advance.

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