how to use LPC11C24 SPI as shift register?

[lpcware]

Content originally posted in LPCWare by ist-h on Wed Mar 28 02:37:00 MST 2012
Hi all,
is it possible to use the SSP1 of the LPC11C24 as a simple shift register?
We want to plug several devices one after another, to avoid using the slave select. So data will be clocked from the master to the first slave device, data from the first slave to second and so on. And the end of the line the master will receive data from the last slave (SSEL is always low):

==>master==>slave1==>slave2==>...==>slaveX===
||                                                                                         ||
=====================================

With this arragement we build a time controlled system: The master clocks x times, so he can send slave specific data to every slave. After x-clock-times the slaves read the received data and write new data to the shift register. The master clocks again x-times to receive the data from the slave.
As a consequence the slaves have to be able to shift the data trough without affecting the received data and the timing.

AFAIK the LPC11C24 SSP has to registers: one for received data and one for transmit data. The received data is stored in the receive FIFO and the transmit data will be read from transmit FIFO, even if it is empty?

The question is now: Is it possible to bypass the FIFOs to realise a real shift register?

[lpcware]

Content originally posted in LPCWare by ist-h on Tue Apr 10 03:03:22 MST 2012
No the loopback mode is turned off (LBM bit in SSP1CR1 set to 0).

We have tested the suggestion of NXP_Europe again: The data is not shifted trough the controller if there's no SS, the MISO pin remains high (inactive). If there's a slave select and no data written to txFIFO, the MISO pin goes to an active (low) state as long as SS is active.

[lpcware]

Content originally posted in LPCWare by ukmeterman on Fri Apr 06 10:07:35 MST 2012
Hi,
Have a look through http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0194g/I1005336.html it is the actuall SSP block. Do you have the internal loopback turned on?

[lpcware]

Content originally posted in LPCWare by ist-h on Fri Mar 30 00:39:19 MST 2012
Yesterday we tried to shift 16-bit data trough the register of the controller as you proposed. The data is not shifted out via the MISO. At first we assumed a hardware error. Another evaluation board showed the same result. (We have 2 LPC11C24 LPCXpresso boards).

Following behavior:
If there's no SS no data (0x0000) is shifted out. Neither if data is shifted into the slave nor if data is writen by slave software into the register.
If there's a SS data is received by the slave and data from the register is shifted out. If there's no data in the transmit FIFO, 0x0000 is shifted out.

Another solution could be: If we poll the receive FIFO and if there's new data we write it to the transmit FIFO to be transmited with the next clock cycle. We want to use a bit rate of 500kbit/s, so have to write the data within 2us to the transmit FIFO. We measured a time of around 500ns for this (including setting and resetting a port with: LPC_GPIO0->MASKED_ACCESS). how much takes the setting of a pin from this call?
How much time we have to calculate if there's an interrupt call? We have a timer32_1 match interrupt which is called every 1ms. We could reduce the time which is needed by the ISR itself to a few controller cycles.

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Wed Mar 28 11:59:46 MST 2012
Hello ist-h,

That should work. Inside the SPI-block a shift-register is used. When the controller is not writing to this block, the content of the register will not be changed and is shifted out via the MISO.

I did not test it, but I think the clue is the usage of the SS.

Example:
SPI-host is connected to e.g. 3 slaves. The clocks are connected in parallel and the SS connections are made in parallel too.
The host is sending the first two 8 bits via de MOSI with no SS and the last / next 8 bits are send with active SS. Then the Slaves are invited to interchange information.
After that, three dummy SPI-bytes are send and so the data is entering the SPI-master via the MISO.