Run IRQ code in RAM..

[lpcware]

Content originally posted in LPCWare by alanisgp on Wed Mar 14 10:53:12 MST 2012
Hi, I have a query. I am making a bootloader which asynchronously receive data from the file ".bin" through a GPRS modem UART, for obvious reasons Cortex SRAM capacity, need to invoke the IAP to copy the binary image to flash.
When this happens interrupts are disabled and you lose the data to be entered.
The first solution is to use a USART interface, letting the CTS handle the data transfer, while IAP makes a dump of a block of data in flash. The problem with this is the size of internal buffer of USART GPRS modem.
Another solution, with which I am dealing with, is whether access to the flash is not possible when the IAP is copying the data.
How do I map the UART ISR to run in SRAM?.
Leaving this enabled only interruption may continue to attend the arrival of the modem and saving data in SRAM.
GCC compiler rejects the modifier __ attribute__ ((section (". data"))) preceding the code of the ISR.
How do I relocate code in SRAM?
How do I tell the linker the memory location that placed in IVT?

A

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Thu Mar 15 05:00:15 MST 2012
Info on running code from RAM can be found here...

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

With regards to your other questions, would suggest that you check the user manual for the part in question. For example for LPC17xx, it says...

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Quote:
The flash memory is not accessible during a write or erase operation. IAP commands,which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application.

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and

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Quote:
32.3.2.6 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active. The user should either disable interrupts, or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP call. The IAP code does not use or disable interrupts.

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Thus if you want to run your interrupt handler whilst doing the IAP, you are not only going to have to relocate your interrupt handler, but you are also going to have to put a vector table into RAM  and set the VTOR register appropriately (assuming a Cortex-M3/M4 part).

You might also want to search the forum for past threads on IAP.

Regards,
CodeRedSupport.