ADC Sampling time (LPC1317)

[lpcware]

Content originally posted in LPCWare by aamir ali on Sun Mar 24 23:58:52 MST 2013
In adc, there is conversion time & sampling time.
Conversion time is always fixed & sampling time may vary according to source impedance.  Right???????


Now I have to measure battery voltage 12V via LPC. So I am using simple resistor divider of 300K & 100k. So when voltage of 12v appears I get 3V at ADC pin.


Problem is in this case my source impedence, according to thevenin is

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Quote:
Rs = Rth = (100K || 300K)

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But I didn't find anything related to sampling time in LPC datasheet.

How to solve this problem.


Also what's the conversion time.

[lpcware]

Content originally posted in LPCWare by micrio on Mon Mar 25 06:50:50 MST 2013
In the LPC13XX data sheet the ADC input resistance is listed as 2.5M ohms
and 1 pF.   That should help you calculate your loading.

I always wondered what the ADC apature time is.   I assume it is 1 clock
cycle.

Pete.

[lpcware]

Content originally posted in LPCWare by aamir ali on Mon Mar 25 04:59:03 MST 2013
Zero,
I know conversion time is fixed.

Sampling time which datasheet mentions in LPC1317, is mentioned with no source resistor value. So one can assume that for that much of speed no source resistance is used.

But problem occurs when source resistance is high, like in my case. Due to large source resistance the capacitor don't get fully charged if not sampled for enough time.
Generally 8, 16 Bit MCU have this time mentioned,

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Quote:
For example for MSP4330G2553, tsample should be greater than
tsample > (RS + RI) × ln(2^11) × C,

Rs - Rsource,
Ri - input mux resistance
C = cap.

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I have gone through many of ARM documents/other cortex M3 MCU, none have mentioned the sampling time formula.

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Mon Mar 25 02:40:46 MST 2013

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Quote: Aamir Ali
But I didn't find anything related to sampling time in LPC datasheet.

How to solve this problem.

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Read User Manual UM10524 :eek:

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Quote:

20.2 Basic configuration
...
Remark: Basic clocking for the A/D converters is provided by the APB clock. A programmable divider is included in each converter to scale this clock to the clock (maximum 15.5 MHz in 12-bit mode or 31 MHz in 10-bit mode (BURST bit = 0)) needed by the successive approximation process. [COLOR=Red]A fully accurate conversion requires 31 of these clocks.[/COLOR]

20.3 Features
• 12-bit successive approximation Analog-to-Digital Converter (ADC).
• Input multiplexing among 8 pins.
• Power-down mode (see PDRUNCFG register in the SYSCON block (Table 42).
• Low power mode.
• Measurement range VREFN to VREFP (or 0 V to VDD for pin packages without
VREFP and VREFN pins). Do not exceed the VDD voltage level.
[COLOR=Red]• 12-bit conversion rate of 500 kSamples/s.
• 10-bit, double conversion rate mode (up to 1 Msamples/s).[/COLOR]
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.

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