Content originally posted in LPCWare by Ex-Zero on Fri Mar 16 02:52:07 MST 2012
Quote:
The maximum ADC sampling rate is 4.5MHz according to the datasheet.
No :)
That's 'the clock for the ADC' as described in User Manual 10398:
Quote:
The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
To calculate the maximum sampling rate you have to divide this clock with the number of clocks of your ADC setting:
11 clocks / 10 bits
10 clocks / 9 bits
9 clocks / 8 bits
8 clocks / 7 bits
7 clocks / 6 bits
6 clocks / 5 bits
5 clocks / 4 bits
4 clocks / 3 bits
So for a 10bit conversion with 4.5MHz ADC frequency you need >2.44µs = <409 kHz sampling rate :)
Quote:
What is the minimum sampling rate?
There's no minimum sampling rate. You can use whatever you want to trigger your ADC. A slow timer or Halley's Comet :rolleyes:
