Content originally posted in LPCWare by NXP_USA on Wed Apr 06 10:37:41 MST 2011
Hello Kartman,
Please be aware that the LPC122x devices are [B]NOT[/B]specified to operate at [B]48MHz[/B], and what you are attempting is technically operating the part beyond it's guaranteed operating conditions.
From the datasheet:
"...running at frequencies of up to [B]45 MHz[/B] (one wait state from flash) or [B]30 MHz[/B] (zero wait states from flash)."
Also please pay attention to the fact that operating at frequencies above 30MHz requires that you enable two cycle read timing. The start up code does this with the following block (however if you are changing frequencies at run time outside of SystemInit(), you may need to perform this task manually):
#if (__SYSTEM_CLOCK > 30000000)
/*
Enable 2 cycle reads for high frequency operation
Must be done prior to setting up PLL
*/
LPC_FLASHCTRL->FLASHCFG = 0;
LPC_SYSCON->PRESETCTRL &= ~(1<<15);
#endif
I realize that 30 and 45MHz are not a native multiples of the 12MHz clock sources (IRC, Crystal on LPCXpresso boards), however you can use the System AHB clock divider (LPC_SYSCON->SYSAHBCLKDIV) to post divide a higher PLL frequency down to be within spec.
The subtlety in operating at these frequencies is the reason the LPCXpresso examples use 24MHz, as they are the highest native multiple of the XTAL and IRC which will operate with single cycle read timing.
If you have further questions please don't hesitate to ask.
