lpcware

LPC1114: confusion about UART example

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by RA1981 on Sun Mar 27 01:29:37 MST 2011
Hi,

I'm going through the examples provided with the LPCxpresso IDE.
Currently I'm looking at the UART example located in the "UART" folder, sub-folder "driver", file "UART.c".
The interrupt handler has the following RLS (receive line status) section:

  if (IIRValue == IIR_RLS)        /* Receive Line Status */
  {
    LSRValue = LPC_UART->LSR;
    /* Receive Line Status */
    if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
    {
      /* There are errors or break interrupt */
      /* Read LSR will clear the interrupt */
      UARTStatus = LSRValue;
      Dummy = LPC_UART->RBR;    /* Dummy read on RX to clear
                                interrupt, then bail out */
      return;
    }
    if (LSRValue & LSR_RDR)    /* Receive Data Ready */           
    {
      /* If no error on RLS, normal ready, save into the data buffer. */
      /* Note: read RBR will clear the interrupt */
      UARTBuffer[UARTCount++] = LPC_UART->RBR;
      if (UARTCount == BUFSIZE)
      {
        UARTCount = 0;        /* buffer overflow */
      }   
    }
  }
If I understand the LPC11xx User Manual correctly, the only interrupt source for RLS interrupts are the error flags OE, PE, FE and BI of the Line Status Register LSR.
Now, the confusion is about the second if-block which checks the receive data ready flag RDR. If the above mentioned error flags are the only source for a RLS interrupt, the second if-block could never be executed because the condition for the first if-block is true and therefore the ISR is leaved.
What am I missing?

There's also a confusing statement in the user manual regarding the RDA interrupt source:
"Rx data available [B]or[/B] trigger level reached in FIFO (U0FCR[0]=1)"
According to UART FIFO Control Register (U0FCR) description U0FCR[0] (FIFOEnable flag) must not be zero when using the UART. So the above could be missunderstood in a way that the FIFO trigger level is useless...
I [U]think[/U] I can read it as:
"Rx data available[B](U0FCR[0]=0)[/B] or trigger level reached in FIFO (U0FCR[0]=1)"
Am I correct?

Sorry if I'm asking silly questions, but for me it seems NxP user manuals are hard to read, they should be more detailed :(

Regards,

Ralf

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