SPI read pauses

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

SPI read pauses

206 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by JSalisbury on Tue Aug 09 01:58:38 MST 2011
I am wanting to read 24 bits from the SPI bus and I am doing so as 3 bit reads as per the code below. The SPI clock speed is 5.5MHz, the processor clock is 49.5 MHz I am finding there are 2.2us pauses between the reads, any ideas on how to reduce these?

  for ( i = Length ; i > 0; i-- )  // changed to count down
  {
     LPC_SSP0->DR = 0xFF;
    /* Wait until the Busy bit is cleared */
      while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
 *buf = LPC_SSP0->DR;
      buf++;
    }


Thanks
0 Kudos
1 Reply

186 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rob65 on Tue Aug 09 04:09:42 MST 2011
J,

while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
waits for the SPI to be not busy and the receive FIFO not empty.

Another thing is that the SPI also generates a SSEL signal that becomes  high in between two frames, so there will always be some delay in between the words you send. (see fig. 42, page 260 in UM10375 rev 3, the latest lpc13xx user manual)

This means that you are not using the FIFO and after sending each set of clock pulses you are waiting for the SPI bus to be no busy anymore (i.e. the SSEL is high again).

To get your speed as fast as possible, use the FIFO and use large word sizes to have less delays as possible.
You could set the data size to 12 bits to read 2 x 12 bits, this will give you only 1 delay in between the bits.

If you want to read 24 bits, set the data size to 12 bits and just perform two writes to SSP0->DR before waiting for the SSP to become not busy.

I assumed you are using an lpc13xx variant.
If it is an lpc11xx, look at fig. 22 at page 149 of UM10398 or for the lpc17xx, fig 77 at page 415 or UM10360.

Rob
0 Kudos