lpcware

SSP, timeout, RTMIS LPC1768

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by ikoria on Fri Aug 24 01:03:38 MST 2012
Hi all
I can't find some informations.
I'll use SSP1 device as SPI, on LPC1768 device (Cortex-M3)

In case of reception, there are 3 IRQs:
-FIFO half full : then I can read 4 frames (4 to 16 bits).
-FIFO over run: then one data is lost...
-FIFO timeout:..

In the UserManual of the LPC17xx, we could find this:

          [B]Quote:[/B]                 
This bit is 1 if the Rx FIFO is not empty, has not been read for a
"timeout period", and this interrupt is enabled. The timeout period is the
same for master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1])
       

I'm afraid that if I work with 4 Bytes blocks, timeout IRQ occurred before the half full IRQ.
Could say me if i'm right?

In User manual for LPC2148, I found this:

          [B]Quote:[/B]                 
This bit is 1 when there is a Receive Timeout condition and this  interrupt is enabled. Note that a Receive Timeout can benegated if  further data is received.
       

With the last definition (but the wrong device), i could be sure that if  i send 4 Bytes, i'll have half_full IRQ and not timeout...

I'm really confused...

Tanks in advance for your response.
Iko

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