25MHz out an compare output pin

[lpcware]

Content originally posted in LPCWare by hzrnbgy on Sat Sep 10 15:04:57 MST 2011
I was wondering if its possible to generate a clean 25MHz, 50% duty cycle waveform using a 32 bit timer assuming I have a clock source of 48MHz

I am considering using this method instead of a separate crystal oscillator to drive an Ethernet chip.

(48MHz) SYSCLK --> SYSAHBCLKDIV(divide by 1)

48MHz --> 32 bit timer

PresCale register=0, TC incremented every PCLK

MR0 = 25000000
MR1 = 12500000

reset TC on MR0 match

thanks

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sun Sep 11 03:29:17 MST 2011

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Quote: hzrnbgy
...or was it 48000000/(4+1)=....

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In fact MR0=2 and MR1=1 is generating 16MHz, so MR0+1 is correct :)

Note: MR0=1 and MR1=1 is creating a 24MHz signal which looks as awful as the 24MHz CLKOUT signal  :mad:

[lpcware]

Content originally posted in LPCWare by hzrnbgy on Sun Sep 11 02:29:51 MST 2011
aha! messed up really bad on the calculation. embarrasing :(

if MR0=4
MR1=2

thats around 48000000/4=12MHz 50% duty cycle?

or was it 48000000/(4+1)=....

I was thinking of a 50MHz sysclk but theres no way I can generate that using the 12MHz IRC.

Oh well, looks like I can't get away with an external crystal

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sat Sep 10 20:50:32 MST 2011
Congratulation,

your calculation is generating a nice 0.52 Hz signal :)

Running with 1/48E6:

f = 1/48E6 * MR0 = 0.52 Hz

Timers are too slow to generate a signal with this frequency.

If you change your main clock to 50MHz you could use CLKOUT to generate a 25MHz output, but that's no 'clean 25MHz, 50% duty cycle waveform' :mad: