lpcware

LPC1225 and PLL problem

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by krzysztofciesluk on Thu Sep 20 01:57:51 MST 2012
Hello,
I have lpc1225 and System Oscillator 14,7456 MHz.
I enable 2 cycle reads for high frequency operation

LPC_FLASHCTRL->FLASHCFG = 0;
LPC_SYSCON->PRESETCTRL &= ~(1<<15);
/* Wait 200us for OSC to be stablized, no status indication, dummy wait. */
for (i = 0; i < 200; i++) __NOP();

next I set System oscillator as PLL input

REG_SYSCON_SYSPLLCLKSEL = PLL_CLK_SEL_SYS_OSC;
REG_SYSCON_SYSPLLCLKUEN |= PLL_CLK_ENA_UPDATE;
REG_SYSCON_SYSPLLCLKUEN &= ~PLL_CLK_ENA_UPDATE;
REG_SYSCON_SYSPLLCLKUEN |= PLL_CLK_ENA_UPDATE;
while (!(REG_SYSCON_SYSPLLCLKUEN & PLL_CLK_ENA_UPDATE));
for (i = 0; i < 200; i++) __NOP();

next I set M = 3 and P = 2
F(CLKOUT) = 44,2368 MHz = (3 * 14,7456  MHz) = (176.9472 MHz / (2 * 2))

REG_SYSCON_SYSPLLCTRL = (1<<5) |(2<<0);
REG_SYSCON_PDRUNCFG &= ~PDRUNCFG_SYSPLL_PD;
while (!(REG_SYSCON_SYSPLLSTAT & PLL_LOCK));
for (i = 0; i < 200; i++) __NOP();

now I select main clock = pll output

REG_SYSCON_MAINCLKSEL = MAIN_CLK_SEL_PLL_OUT;
REG_SYSCON_MAINCLKUEN |= MAIN_CLK_UPDATE_ENA;
REG_SYSCON_MAINCLKUEN &= ~MAIN_CLK_UPDATE_ENA;
REG_SYSCON_MAINCLKUEN |= MAIN_CLK_UPDATE_ENA;
while (!(REG_SYSCON_MAINCLKUEN & MAIN_CLK_UPDATE_ENA));
for (i = 0; i < 200; i++) __NOP();

And it don't work. I get HardFault or MEM error.
But when i Power-up SYSPLL at the begining of code (after set 2 cycle read) it work

LPC_FLASHCTRL->FLASHCFG = 0;
LPC_SYSCON->PRESETCTRL &= ~(1<<15);
for (i = 0; i < 200; i++) __NOP();

REG_SYSCON_PDRUNCFG &= ~PDRUNCFG_SYSPLL_PD;
while (!(REG_SYSCON_SYSPLLSTAT & PLL_LOCK));

REG_SYSCON_SYSPLLCLKSEL = PLL_CLK_SEL_SYS_OSC;
REG_SYSCON_SYSPLLCLKUEN |= PLL_CLK_ENA_UPDATE;
REG_SYSCON_SYSPLLCLKUEN &= ~PLL_CLK_ENA_UPDATE;
REG_SYSCON_SYSPLLCLKUEN |= PLL_CLK_ENA_UPDATE;
while (!(REG_SYSCON_SYSPLLCLKUEN & PLL_CLK_ENA_UPDATE));
for (i = 0; i < 200; i++) __NOP();


REG_SYSCON_SYSPLLCTRL = (1<<5) |(2<<0);
while (!(REG_SYSCON_SYSPLLSTAT & PLL_LOCK));
for (i = 0; i < 200; i++) __NOP();

REG_SYSCON_MAINCLKSEL = MAIN_CLK_SEL_PLL_OUT;
REG_SYSCON_MAINCLKUEN |= MAIN_CLK_UPDATE_ENA;
REG_SYSCON_MAINCLKUEN &= ~MAIN_CLK_UPDATE_ENA;
REG_SYSCON_MAINCLKUEN |= MAIN_CLK_UPDATE_ENA;
while (!(REG_SYSCON_MAINCLKUEN & MAIN_CLK_UPDATE_ENA));
for (i = 0; i < 200; i++) __NOP();

Is it ok to use that order? Or is it possible that on some board on my desk it will work but on another 100 devices it will not work correct?

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