Content originally posted in LPCWare by mengxp on Sun Jun 12 23:01:19 MST 2016
void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed)
{
/* compute SD/MMC clock dividers */
uint32_t div;
div = ((clk_rate / speed) + 2) >> 1; <<< div here compute wrong
when I set speed=51MHz, div result is = 3.
so SD clock acturally be set at 204MHz / (2*3) = 34MHz.
SD bandwidth = 34M * 4 / 8 = 17MB/s
and test result is:
card_init
clk_rate: 204000000
speed: 20000000
div: 6
clk_rate: 204000000
speed: 51000000
div: 3
speed: 51000000
clk_rate: 0
Speed testing...
Read Speed: 14075 KB/s
I correct above bug code
div = (clk_rate / speed) >> 1;
so div will be set to 2 correctly, SD clock will be set at 204MHz / 2*2 = 51MHz
SD bandwidth = 51M * 4 / 8 = 25.5MB/s
and test result is
card_init
clk_rate: 204000000
speed: 20000000
div: 5
clk_rate: 204000000
speed: 51000000
div: 2
speed: 51000000
clk_rate: 0
Speed testing...
Read Speed: 19621 KB/s
see? that is a big improve!
And why the Mass Storoge example run at a bad performance about:
Read: 7MB/s
Bacause this example use a synchronous SD Read/Write
So read/write performance will be cut about a half.
Use double buffer and asynchronous SD read/write will do better performance
