Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) { uint32_t Status; Status = Chip_SPI_GetStatus(pSPI); /* Check error in STAT register */ if (Status & (SPI_STAT_RXOV | SPI_STAT_TXUR)) { /* Clear errors */ Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR); return ERROR; } if (pXfSetup->TxCnt == 0) { if (pXfSetup->pRx == NULL) { Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, pXfSetup->ssel | SPI_TXCTL_EOF | SPI_TXCTL_RXIGNORE); } else { Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, pXfSetup->ssel | SPI_TXCTL_EOF); } } if (pXfSetup->pRx == NULL) { if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { SPI_Send_Data_RxIgnore(pSPI, pXfSetup); } } else { /* check if Tx ready */ if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { SPI_Send_Data(pSPI, pXfSetup); } /* check if RX FIFO contains data */ if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) { SPI_Receive_Data(pSPI, pXfSetup); } } return SUCCESS; } |
// This needs to be an array of words... // uint16_t rx_buff[100]; <snip> // Note the type changes here as well... // uint8_t SPIReceiveByte(uint8_t data) { // Must send a pointer to a word to WriteSpiMssg. // put the value to send in a word. // uint16_t wordToSend = data; // Pass the address of wordToSend (the pointer to wordToSend). // WriteSpiMssg( &wordToSend, 1); return (uint8_t) rx_buff[0]; } |
/* Interrupt error code (used as semaphore) */ static volatile int intErrCode; /* SPI Transfer Setup */ static SPI_DATA_SETUP_T spi1Setup; uint8_t rx_buff[100]; void WriteSpiMssg(uint16_t *xferPtr, uint32_t xferSize) { /* Init variable used as semaphore */ intErrCode = -1; // Setup Transfer structure, this data should be retained for the entire transmission spi1Setup.pTx = xferPtr;//Transmit Buffer spi1Setup.pRx = rx_buff;//Receive Buffer spi1Setup.DataSize =8;//Data size ( bits) spi1Setup.Length = xferSize;//total frame length spi1Setup.ssel = SPI_TXCTL_ASSERT_SSEL0 | SPI_TXCTL_DEASSERT_SSEL1 | SPI_TXCTL_DEASSERT_SSEL2 | SPI_TXCTL_DEASSERT_SSEL3; //assert SSEL0 spi1Setup.TxCnt = 0; spi1Setup.RxCnt = 0; if (Chip_SPI_Int_RWFrames(LPC_SPI1, &spi1Setup) == ERROR) { errorSPI(); } Chip_SPI_Int_Cmd(LPC_SPI1, SPI_INTENSET_RXRDYEN | SPI_INTENSET_TXRDYEN | SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN, ENABLE); // Enable Interrupt when receiver data is available // Enable Interrupt when the transmitter holding register is available. // Enable Interrupt when a receiver overrun occurs // Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only) /* Sleep until transfer is complete, but allow IRQ to wake system to handle SPI IRQ */ while (intErrCode == -1) { __WFI(); } uint8_t SPIReceiveByte(uint8_t data) { WriteSpiMssg(data, 1); return *rx_buff; } void SPI1_IRQHandler(void) { uint32_t i; if (spi1Setup.RxCnt < spi1Setup.Length) { /* Call driver function until transmission is complete */ if (Chip_SPI_Int_RWFrames(LPC_SPI1, &spi1Setup) == ERROR) { errorSPI(); } } else { /* Disable interrupts after transmission is complete */ Chip_SPI_Int_Cmd(LPC_SPI1, SPI_INTENSET_RXRDYEN | SPI_INTENSET_TXRDYEN | SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN, DISABLE); intErrCode = (int) LPC_OK; } } } |
uint8_t SPIReceiveByte(uint8_t data) { WriteSpiMssg(data, 1); return *rx_buff; } |