Non-Open-Drain output 5V tolerance

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by MarcVonWindscooting on Sun Dec 22 16:28:53 MST 2013
Hey guys,

finally I have my first real PCB based on LPC812 finished - a LED torch light/stoboscope driver 8-)
I want to explore both the LPC800 voltage range and the deep power-down mode. As the upper voltage of the LPC800 does not fit very well neither to 3 NiMH cells (3*1.25V = 3.75V) nor to a Li-Ion cell (4.3V) I decided to power it from a STLQ015XG33 nanopower, low-drop LDO. Some parts of the PCB still run from full supply voltage, i.e. I have to interface between two voltage levels, let's say from 3.3V (LPC800) to/from 5V levels (from an IR-receiver).
I have 2 indicator LEDs. One of those is driven by PIO0_7 and it's tied to +5V with a 1.3k resistor. Once PIO0_7 switches low the LED is on - OK.
Now comes the interesting part: How can I switch this LED off? Open-drain would be the way to go, right?

The LPC81XM data sheet states the following for P0_7: Table 4, footnotes:
[2] 5V tolerant pad providing I/O functions with configurable pull-up/pull-down resistors and....

However, the user manual gives me this hint: 6.4.4 (Open-drain mode) :
... This mode is not a true open drain mode. The input cannot be pulled above Vdd.
(That leaks considerable current through the LED - it does not completely turn off)

Now how can this both be true? Either the circuit is 5V tolerant, meaning it may be pulled up to 5V or it isn't and I only have a 3.3V open-drain (emulation).

Some experimenting showed, that it is really like that: if configured as input (pull up/down/repeater disabled), PIO0_7 is high impedance, even with the LED at 5V. If PIO0_7 is configured as output - standard output, it it always sinks current if the output tries to go above Vdd (LED never switching completely off).
So setting the PIO0_7 output register to 0 and switching between input and output gives me the desired 5V (minus the LED-drop) tolerant 'open drain'. Why the hell isn't that possible in the open-drain mode in the first place?

I don't feel very comfortable with this trick and I assume something goes wrong here as soon as I enter deep power-down.
Why not publish the 'real' schematic of the outputs? What does NXP mean by a FET with an inverter circle on its gate (6.4.1, the upper FETs)? N-channel depletion? P-channel enhancement? What about the substrate??