LPC 824 DMA error bit set

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 7, 2018 by michael boyko
Content originally posted in LPCWare by aimer on Thu May 28 04:49:14 MST 2015
I'm implementing a small SW application using LPCxpresso, version 7.6.2 on a LPC824. There is a problem using the DMA controller. In the application, the DMA controller is used  to write 4 32 bit values continously in the background from a memory array to the GPIOs via the masked pin register (MPIN0).

In the Error Interrupt Status Register of the DMA controller, I always got the error interrupt bit set. The users manual describes how to reset this bit. If I do this, it will be set again when the next DMA trigger event happens. The trigger comes from the SCT_DMA0 with a frequency of 4 khz. What are possible reasons to set this error interrupt bit? There is nothing in the users manual about this?

The DMA buffer descriptors are used in the ping-pong technique as described in the users manual. I checked the aligment of the initial descriptor (512) and the 2 'ping-pong' descriptors as well as the pointers in the descriptor. Anything seems to be OK. In the Channel specific transfer configuration register the bit field 'XFERCOUNT' is decremented from 3 to 2  so I assume that the DMA channel is stopped at the first transfer due the error condition which leads to set the error interrupt status bit. Again, to find out what's going wrong, it would be helpful to know, what the reasons for setting the error interrupt bit are? Can anyone help?