PLL Setup question

[lpcware]

Content originally posted in LPCWare by Floyd42 on Mon Jan 13 13:53:16 MST 2014
Hi,

I'm wondering about the PLL setup. The manual says:

* PLL on  (PDRUNCFG, SYSPLLCTRL)
* wait untils stable (SYSPLLSTAT)
* set main clock to PLL (MAINCLKSEL)
* set divider (SYSAHBCLKDIV)

And this works well. But I wonder why it works actually?

After MAINCLKSEL is written, SYSAHBCLKDIV is still invalid with the value "1" and so in my case the core would get 60 MHz until a value "2" is placed there to make it 30 MHz, the max. allowed value. So what happens here that this works? Does the core loose some clocks and thus runs a bit undefined for these few cycles? Or do all these changes take some time to settle internally anyway? Is there and internal overclocking protection? And curiously, how many code can be placed between setting MAINCLKSEL and setting SYSAHBCLKDIV to be still safe?

Thanks, Axel

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Mon Jan 13 16:00:51 MST 2014
Hi Axel,

I believe it's working in your case, because your controller stands over-clocking at least for a short time.
I'm rather sure, NXP does not waste silicon on 'fixing programming bugs'-circuits, if they don't give us more than only 2 states in the SCT...

The manuals are a bit sloppy sometimes.
But you'll notice that the different chapters of the manual do not assume RESET defaults as a starting point. For example deasserting of peripheral resets is described, even if the reset default is 'RESET deasserted'. Same with PDAWAKECFG.

Follow your intuition and change the order of the statements - don't over-clock that happy little device :((