PLL Setup question

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Floyd42 on Mon Jan 13 13:53:16 MST 2014

I'm wondering about the PLL setup. The manual says:

* wait untils stable (SYSPLLSTAT)
* set main clock to PLL (MAINCLKSEL)
* set divider (SYSAHBCLKDIV)

And this works well. But I wonder why it works actually?

After MAINCLKSEL is written, SYSAHBCLKDIV is still invalid with the value "1" and so in my case the core would get 60 MHz until a value "2" is placed there to make it 30 MHz, the max. allowed value. So what happens here that this works? Does the core loose some clocks and thus runs a bit undefined for these few cycles? Or do all these changes take some time to settle internally anyway? Is there and internal overclocking protection? And curiously, how many code can be placed between setting MAINCLKSEL and setting SYSAHBCLKDIV to be still safe?

Thanks, Axel