Chip_DMATRIGMUX_SetInputTrig(LPC_DMATRIGMUX, DMA_CH0, DMATRIG_ADC_SEQA_IRQ); |
// Setup DMA for ADC /* DMA initialization - enable DMA clocking and reset DMA if needed */ Chip_DMA_Init(LPC_DMA); /* Enable DMA controller and use driver provided DMA table for current descriptors */ Chip_DMA_Enable(LPC_DMA); Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table)); /* Setup channel 0 for the following configuration: - High channel priority - Interrupt A fires on descriptor completion */ Chip_DMA_EnableChannel(LPC_DMA, DMA_CH0); Chip_DMA_EnableIntChannel(LPC_DMA, DMA_CH0); Chip_DMA_SetupChannelConfig(LPC_DMA, DMA_CH0, (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGTYPE_EDGE | DMA_CFG_TRIGPOL_HIGH | DMA_CFG_BURSTPOWER_1 | DMA_CFG_CHPRIORITY(0) )); // Attempt to use ADC SEQA to trigger DMA xfer Chip_DMATRIGMUX_SetInputTrig(LPC_DMATRIGMUX, DMA_CH0, DMATRIG_ADC_SEQA_IRQ); DMA_CHDESC_T dmaDesc; /* DMA descriptor for memory to memory operation - note that addresses must be the END address for src and destination, not the starting address. DMA operations moves from end to start. */ dmaDesc.source = DMA_ADDR ( (&LPC_ADC->DR[3]) ); // ADC channel 3 data register is source dmaDesc.dest = DMA_ADDR(&dst[SIZE_BUFFERS - 1]) + 3; dmaDesc.next = DMA_ADDR(0); /* Enable DMA interrupt */ NVIC_EnableIRQ(DMA_IRQn); /* Setup transfer descriptor and validate it */ Chip_DMA_SetupTranChannel(LPC_DMA, DMA_CH0, &dmaDesc); Chip_DMA_SetValidChannel(LPC_DMA, DMA_CH0); /* Setup data transfer and software trigger in same call */ // See "Transfer Configuration registers" table 173 §12.6.18 page 179 Chip_DMA_SetupChannelTransfer(LPC_DMA, DMA_CH0, ( DMA_XFERCFG_CFGVALID // Channel descriptor is considered valid | DMA_XFERCFG_SETINTA // | DMA_XFERCFG_SWTRIG // When written by software, the trigger for this channel is set immediately. | DMA_XFERCFG_WIDTH_32 // 8,16,32 bits allowed | DMA_XFERCFG_SRCINC_0 // do not increment source | DMA_XFERCFG_DSTINC_1 // increment dest by widthx1 | DMA_XFERCFG_XFERCOUNT(SIZE_BUFFERS) ) ); |